Function level reset (flr), Clocks, Clock domains – Altera Stratix V Avalon-ST User Manual
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For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.
Function Level Reset (FLR)
The following sequence of events occurs after a FLR to a Physical Function:
1. The host stops all traffic from and to the Function.
2. The host writes the FLR bit in the
Device Control
Register to trigger the FLR reset.
3. The SR-IOV Bridge resets R/W non-sticky control bits in the Configuration Space of the Function. It
notifies the Application Layer via
flr_active_*
signals.
4. The Application Layer cleans up all state related to the Function. It asserts FLR Completed via
flr_completed_*
signal. The Application Layer should either discard all pending requests from the
Function, or send Completions. If the Application Layer sends Completions, the host drops them
without checking for errors.
5. The SR-IOV Bridge re-enables the Function by deasserting the
flr_active_*
signal associated with
this function.
6. The host re-enumerates the Function.
This handshake ensures that the Completion for a request issued before the FLR does not return
after the FLR is complete.
Related Information
Function-Level Reset Interface
Clocks
The Hard IP contains a clock domain crossing (CDC) synchronizer at the interface between the
PHY/MAC and the DLL layers. The synchronizer allows the Data Link and Transaction Layers to run at
frequencies independent of the PHY/MAC. The CDC synchronizer provides more flexibility for the user
clock interface. Depending on parameters you specify, the core selects the appropriate
coreclkout_hip
.
You can use these parameters to enhance performance by running at a higher frequency for latency
optimization or at a lower frequency to save power.
In accordance with the PCI Express Base Specification, you must provide a 100 MHz reference clock that is
connected directly to the transceiver.
As a convenience, you may also use a 125 MHz input reference clock as input to the TX PLL.
Related Information
Clock Domains
UG-01097_sriov
2014.12.15
Function Level Reset (FLR)
6-5
Reset and Clocks
Altera Corporation