Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 94)

7–12 Quartus II Version 3.0 Altera Corporation
Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide
The error detection block monitors the output of the edge detection
module and the match register. If match goes low while data is valid, the
error register is set. The error counter also increments every clock cycle
that an error is detected. The count value is converted to decimal values
for display. The counter rolls over at 99 to 0 and then increments. Pressing
the reset signal clears the error register and resets the counter to 0.
Stratix GX HM-Zd (SPI-4.2)
This section describes the Stratix GX HM-Zd (SPI-4.2) test. Refer to
“Source Synchronous HM-Zd Interface (Stratix GX HM-Zd SPI 4.2)” on
page 5–14 for information on how to perform the test.
Stratix GX HM-Zd (SPI-4.2) Test Overview
This design has a PLL, an LVDS transmitter and receiver, and a
Verilog HDL block with the logic required to generate a PRBS and verify
that it was received correctly. The design uses two HM-Zd loopback
cards to complete the circuit. The pinout is compatible with the SPI-4.2
standard, including the high-speed control signal and the low-speed
status signals.
You can use the top-level BDF to modify the system clock rate as desired
to emulate a particular system configuration. By varying the system clock
PLL and LVDS megafunction parameters, you can adjust the per channel
data rate from 300 to 1,000 Mbps. This design uses the DPA feature of the
Stratix GX family to boost the data rate to 1,000 Mbps.
The design has a Verilog HDL wrapper to name and place all of the pins
and to provide proper termination for the LVDS signals. The Stratix GX
pushbutton switches control the data transmission (start and stop), insert
errors, and reset the circuit. The LEDs indicate the start of transmission,
the start of reception of valid data, confirmation that correct data was
received, error status, and the reset condition.
The main system clock (parallel data rate) is derived from the 33-MHz
crystal oscillator using a 15/4 ratio resulting in 125-MHz clock rate. The
data is generated in 8-bit words per channel using a PRBS generator with
a repetition count of 31, resulting in a serial data rate of 1 Gbps. The data
is then sent to a 17-channel version of the Altera LVDS megafunction,
which uses a high-speed PLL and a SERDES block to convert the data into
serial data streams. The LVDS megafunction also generates the transmit
clock, which is 125 MHz. You can vary the clock speed by changing the
parameters of the LVDS megafunction.