Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 90)

7–8 Quartus II Version 3.0 Altera Corporation
Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide
300 to 840 Mbps. The design has a Verilog HDL wrapper to name and
place all of the pins and to provide proper termination for the LVDS
signals.
The Stratix design is a BDF with the LVDS receiver and transmitter blocks
implemented using the Altera MegaWizard
® Plug-In Manager. When
you vary the Stratix GX data rates, you must adjust the Stratix data rates
accordingly.
The main system clock (parallel data rate) is derived from the 33-MHz
crystal oscillator using a 63/20 ratio, resulting in 105-MHz clock rate.
Stratix GX-to-Stratix Bridge Functional Description
Figure 7–4 shows the logic diagram for the Stratix GX-to-Stratix bridge
design. Figures 7–5 and 7–6 show the Quartus II top-level BDFs.
1
Open the BDFs in the Quartus II software to view greater detail.