Altera High-Speed Development Kit, Stratix GX Edition User Manual
Page 52
5–8
Quartus II Version 3.0
Altera Corporation
Set Up the Board
High-Speed Development Kit, Stratix GX Edition User Guide
12. Attach the one end of the parallel cable to the PC’s parallel port if it
is not already attached.
13. Connect one end of the ByteBlaster II cable to the parallel cable.
14. Connect the other end of the ByteBlaster II cable to the JTAG header
(J87) on the Stratix GX development board, as shown in Figure 5–12.
Align the red edge of the cable with pin 1.
Figure 5–12. Attach the ByteBlaster II Cable
15. Move the power selection switch (SW3) to the middle position (off).
16. Attach the main power cable from the ATX supply to the power
connector (J31) on the board.
17. Set the Stratix bypass (SW1) and Stratix GX bypass (SW2) switches
to NO.
18. Set the configuration switch (SW4) to PS_HDR as shown in
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
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- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
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- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
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- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
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- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
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- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
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- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
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- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
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- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)