Altera High-Speed Development Kit, Stratix GX Edition User Manual
Page 77
Altera Corporation
Quartus II Version 3.0
5–33
Perform the Production Diagnostic Tests
Nios-Based Tests
Figure 5–24. Installed Compact Flash Card
3.
Change the programming file for the Stratix device to the
cf_1s40.sof
file. Wait until the checksum field is updated.
4.
Turn on the Program/Configure option for the Stratix device.
5.
Click Start. When configuration is complete, the S_CONF_DONE
LED illuminates.
6.
Choose Programs > Altera > SOPC Builder <version> > SOPC
Builder SDK Shell
(Windows Start menu).
1
This shell may be named Nios SDK Shell in older versions
of the Nios embedded processor.
7.
Change to the Nios SOFs directory by typing the following
command:
cd /Stratix_GX_kit/Test_designs/Nios_test_designs/
Nios_sofs
r
8.
Type
nr -t
r to open a terminal window that connects to COM 1.
9.
Press the Enter key twice in the terminal window. You should be at
a Nios prompt.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)