Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 113)

Altera Corporation Quartus II Version 3.0 7–31
Diagnostic Test Details Standard Tests
The transmit packet generator is a Verilog HDL module. When enabled,
the module generates simple XGMII style packets, otherwise, it outputs
idle characters. An XGMII packet consists of a header, data payload and
a termination character sequence. The data is created as a series of octets
of bytes (64 bits) and an 8-bit wide control word. Each bit in the control
word corresponds to one of the bytes in the octet. The data payload is the
output of an 8-bit counter. The packet generator also inserts an
interpacket gap between packets. The packet size and interpacket gap
size is hard-coded in the Verilog HDL code.
The design has a control block that monitors the pushbuttons and status
to control the test operation. Because this test is using the XAUI and
XGMII protocols, the GXB megafunction channels must be synchronized
and aligned to each other. The control block monitors this
synchronization and allignment, and illuminates LED1 when the
channels are synchronized and LED2 when they are aligned. The control
block also prevents the start of the test until the channels are aligned.
When you press PB0 to start the test, the control logic checks the status of
the channel and triggers the packet generator to start. It also illuminates
LED4.
The data from the packet generator is sent to the GXB transmit block
created using the Altera MegaWizard Plug-In Manager. The
megafunction is configured with the XAUI protocol using four channels
running at 3,125 Mbps with an input clock rate 156.25 MHz. The GXB
megafunction takes the data stream along with the control character
information and converts the data from XGMII protocol to XAUI
protocol, including 8B/10B encoding of the data stream. The signals are
then sent to the XPAK module and looped back to the Stratix GX device
using the optical loopback fiber.
The receive portion of the GXB megafunction on the Stratix GX device
converts the serial data back to parallel 64-bit words. The data is then
passed to the pattern detector to determine the start of the data packet.
When the pattern detector detects the synchronization pattern twice, it
sets the data valid signal and begins passing the data to the comparator.
The data valid signal also drives LED3.
A second packet generator uses the data valid signal to start generating
the expected data values. This second data set is sent to the comparator.
The comparator module takes the output from the pattern detector block
and compares it with the output from the receive channel packet
generator. The 64-bit words are compared each clock cycle during the
data payload section of the data stream. The comparator output is high if
the words match. The output from the comparator is stored in a single-bit
match register. The output of this register drives the match LED.