Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 124)

7–42 Quartus II Version 3.0 Altera Corporation
Nios Designs High-Speed Development Kit, Stratix GX Edition User Guide
Figure 7–20. Stratix Nios 10/100 Ethernet Network-Interface Card I/O Logic Diagram
In this design, the Nios processor controls three Avalon bus slave
modules. Although the flash interfaces are part of this design, they are not
used during this test.
The first module handles all of the I/O signals and timing for the
Stratix GX EPC16 configuration device. It controls the data, address, and
controls signals, and reports status to the Nios processor. The second
Avalon bus module controls both the Stratix EPC16 device and the
4-Mbyte on-board flash chip. It is configured with extra address signals
for the on-board flash chip. The third module interfaces with the 10/100
Ethernet network-interface card I/O connector interface.
The 10/100 Ethernet network-interface card I/O test involves running
the hello_plugs program. The test gives two different results depending
on whether the board is attached to a network. If a board is not connected,
the test initializes the chip and looks for the network, but because the
board is not connected, the test generates timeouts. If a board is
connected, the test uses DHCP to get a dynamic IP address for the board.
On-Board
Flash
Stratix GX Address
Stratix GX Data
Stratix Address
Stratix Data
21
Add[20:0]
Data[15:0]
Add[20:0]
Data[15:0]
Add[21:0] Data[16:0]
22
16
16
Stratix Device
Stratix GX
EPC16
Stratix
EPC16
MAC/PHY
(LAN91C111)
Integrated
RJ-45 Connector
40
Status, Data
Control&
RS-232
Port
Avalon
Bus
Inerface
Avalon
Bus
Interface
Avalon
Bus
Interface
Avalon
Bus
Nios
CPU
10/100 Ethernet Network Interface Card