Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 112)

7–30 Quartus II Version 3.0 Altera Corporation
Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide
The module converts the data to a single 10-Gbps optical data stream. The
loopback cable feeds the serial data back to the receive input of the XPAK
device. The XPAK module converts the data back to XAUI format. The
data is converted back into parallel form by the GXB megafunction. The
data is then passed to a pattern detection block to find the start of a data
packet in the data stream. When this pattern is found, the data valid
signal is asserted, which triggers an expected value packet generator to
start. The two data streams are sent to a comparator to generate a match
signal. If the data streams match, the match LED illuminates. Only the
data packets are checked for errors. If the match signal goes low while the
data valid signal is high, the error flag is set and the error counter is
incremented. Pressing the reset button resets the system state, error flag,
and error count.
Stratix GX XPAK XCVR Functional Description
Figure 7–15 shows the XPAK XCVR logic diagram.
Figure 7–15. XPAK XCVR Logic Diagram
The system clock is generated by the GXB megafunction’s transmit PLL
using the 156.25-MHz crystal oscillator as the reference. The PLL
generates a 156.25-MHz clock to clock all of the data generation logic.
4
XPAK
Module
4
4
Optical
Fiber
Foopback
2
XGMII
Packet
Generator
ALTGXB
TX
Transmit Channel
72 4
Start/Stop
Synchronization
Detect/Control
4
8
ALTGXB
RX
Comparator
Receive Channel
64
64
64
Match
Register
Data Valid
Error
Register
Error
Counter
Data Valid
XGMII
Packet
Generator
7-Segment
Display
Error LED
Match LED
Pattern Detect