Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 123)

Altera Corporation Quartus II Version 3.0 7–41
Diagnostic Test Details Nios Designs
Stratix Nios 10/100 Ethernet Network-Interface Card I/O Test
This design is similar to the previous flash/Ethernet test because the card
used for this test has the same MAC/PHY chip that is installed on the
Stratix GX development board. The primary difference between the tests
are the I/O pin assignments. The design is captured in VHDL and has a
VHDL wrapper to control the I/O pin names and placements. Because
this is a processor-based test, the actual test consists of running several
object files on the Nios processor and observing the results in a terminal
window on a PC.
The 10/100 Ethernet network-interface card has the LAN91C111 Ethernet
MAC/PHY chip, which the Nios processor tests. The test initializes the
10/100 MAC/PHY chip and runs a set of Ethernet protocol tests from the
hello_plugs
program. The test results vary depending on whether the
board is plugged into a functional network.
f
Refer to “10/100 Ethernet Network-Interface Card I/O Interface (Stratix
Nios PROTO1 IO)” on page 5–29 for information on how to perform the
test.
Figure 7–20 shows the Stratix Nios 10/100 Ethernet network-interface
card I/O logic diagram for the Stratix device.