Altera High-Speed Development Kit, Stratix GX Edition User Manual
Page 55

Altera Corporation
Quartus II Version 3.0
5–11
Perform the Production Diagnostic Tests
Perform the Standard Tests
3.
Click Auto-Detect. The Stratix, Stratix GX, and 2 EPC16 devices
display in the JTAG chain.
4.
Change the programming file for the Stratix GX device:
a.
Right-click the filename next to the Stratix GX device.
b.
Browse to the standard SOFs directory.
c.
Select the file GX40_User_IO.sof.
d.
Click Open. Wait until the checksum field is updated.
5.
Change the programming file for the Stratix device to
STX40_User_IO.sof
using the steps described above. Wait until the
checksum field is updated.
6.
Turn on the Program/Configure option for the Stratix and
Stratix GX devices. See Figure 5–15.
Figure 5–15. Quartus II Programmer for the User I/O Test
7.
Click Start to configure both devices. When configuration is
complete for both devices, the GX_CONF_DONE (D7) and
S_CONF_DONE (D6) LEDs illuminate as shown in Figure 4–1 on
page 4–2.
8.
Test the user I/O for the Stratix GX device by performing steps 1
through 12 in “Run the User I/O Test” on page 4–3.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)