Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 111)

Altera Corporation Quartus II Version 3.0 7–29
Diagnostic Test Details Standard Tests
high if the words match. The output from each receive channel
comparator is stored in a single bit match register. The output of this
register drives the match LED on a per channel basis.
The error detection and counting blocks monitor the match and data
valid signals. If the match signal goes low while data is valid, the error
flag is set and the error counter is incremented. The reset pushbutton
clears the error flag and resets the counter. The error insertion
pushbutton inverts one bit in each data channel for one clock cycle, which
is enough to trigger the error detection circuit even if only one channel is
active.
Stratix GX XPAK XCVR
This section describes the Stratix GX XPAK XCVR test. Refer to “Gigabit
Transceivers with XPAK Interface (Stratix GX XPAK XCVR)” on
page 5–20 for information on how to perform the test.
1
This test requires an XPAK module, which is not included with
the kit.
Stratix GX XPAK XCVR Test Overview
The XPAK interface design consists of a 4-channel Altera GXB
transmitter/receiver block configured in XAUI mode and a Verilog HDL
block with the logic required to generate a simple XGMII packet stream
and verify that it was received correctly. The design requires an XPAK
module with optical loopback cable to complete the signal loopback.
The top-level BDF lets you easily modify the system clock rate to evaluate
a particular system configuration. The design has a Verilog HDL wrapper
to name and place all the pins and provide proper termination for the
signals. The Stratix GX pushbutton switches control the start and stop of
the data transmission and reset the circuit. The LEDs indicate the start of
transmission, the start of reception of the valid data, confirm that data
was received correctly, error status, and indicate the reset condition.
The main system clock (parallel data rate) is derived from the
156.25-MHz crystal oscillator using the GXB megafunction clock output.
The data is generated as a 64-bit word using a simple packet generator.
The generator creates idle packets and XGMII style packets with a
preamble, data payload, and termination octets. The generator also
inserts an inter packet gap (IPG) between packets, resulting in a serial
data rate of 10 Gbps. The data is then sent to a 4-channel version of the
Altera GXB megafunction configured for the XAUI protocol, which
converts the data into four 3.125-Gbps serial data streams. These streams
are sent to the XPAK module.