Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 102)

7–20 Quartus II Version 3.0 Altera Corporation
Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide
The top-level BDF lets you easily modify the system parameters as
desired to evaluate a particular system configuration. By varying the GXB
megafunction parameters, you can adjust the per channel data rate up to
3,125 Mbps. The design has a Verilog HDL wrapper to name and place all
of the pins and to provide proper termination for the signals. The
Stratix GX pushbutton switches control the start and stop of the data
transmission, insert errors, and reset the circuit. The LEDs indicate the
start of transmission, confirm that data was received correctly, error
status, and the reset condition.
The main system clock (parallel data rate) is derived from the
156.25-MHz crystal oscillator using the GXB megafunction clock output.
The data is generated in 20-bit words per channel using a PRBS generator
with a repetition count of 31, resulting in a serial data rate of 3.125 Gbps.
The data is then sent to a 4-channel version of the GXB megafunction,
which converts the data into gigabit serial data streams. The
megafunction instance uses the basic protocol option.
The SMA cables feed the serial data back to the receive inputs on the
Stratix GX device. The GXB megafunction converts the data back into
parallel. Because the implementation uses the GXB megafunction’s
double word feature, the byte alignment of the received data may be
inaccurate. To adjust it, the data is sent through a byte swap block based
on synchronization data from the GXB megafunction. The data is then
passed to a pattern detection block to find the start of data in the PRBS
(the first word of the PRBS sequence) data stream. When this pattern is
found, the data valid signal is asserted. This assertion triggers an
expected value PRBS generator to start. The two data streams are sent to
a comparator to generate a match signal on a per channel basis. If the data
streams match, the match LED illuminates on a per channel basis. If the
match signal goes low while the data valid signal is high, the error flag is
set and the error counter is incremented. Pressing the reset button resets
the system state, error flag, and error count.
Stratix GX SMA XCVR Functional Description
Figure 7–11 shows the Stratix GX SMA XCVR logic diagram. Figure 7–12
shows the Quartus II top-level BDF for all of the XCVR tests.
1
Open the BDF in the Quartus II software to view greater detail.