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Altera High-Speed Development Kit, Stratix GX Edition User Manual

Page 110

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7–28

Quartus II Version 3.0

Altera Corporation

Standard Tests

High-Speed Development Kit, Stratix GX Edition User Guide

The transmit PRBS generator is constructed with 16 5-bit linear feedback
shift registers. The output is taken from the MSB of each shift register. The
initial seed value is 16’h1A47. When the enable (start) signal is high, the
generator outputs a 31-word sequence that repeats until stopped. On
reset, the seed value is initialized into all registers. This generator
generates the data stream that exercises the system. Each transmit
channel has its own PRBS generator.

The double word option requires synchronization of the control logic
with the GXB receive section. The design uses a 16-bit alignment pattern,
16’h1A47, for synchronization. The design also uses a custom protocol
with manual word alignment. This protocol requires the use of a byte
swap block to align the upper and lower bytes of the 16-bit word. Status
signals from the GXB block control the byte swap circuit on a per channel
basis.

The data from the PRBS generators is sent to the GXB transmit block
created using the Altera MegaWizard Plug-In Manager. The
megafunction is configured as 4 channels running at 2.488 Gbps with an
input clock rate of 155.52 MHz. The signals are then sent to the SFP
module connectors (J54, J64, J45, and J38). You can use either an OC-48
SFP optical module with loopback fiber or the SFP loopback card to
provide the loopback function required to return the data to the Stratix
GX device.

The SFP module has 3 status signals:

TX_Fault, TX_Disable, and

RX_LOS. The TX_Fault and RX_LOS signals are not monitored to allow
the use of the SFP loopback card.

TX_Disable is controlled by the stop

pushbutton. The

MOD-DEF[2:0] signals are not used or monitored in

this design. The Altera SFP loopback card has DC blocking capacitors in
the high-speed data path to preserve the DC levels on the transmit and
receive buffers.

The receive portion of the GXB megafunction converts the serial data
back to parallel 16-bit words. The received data is sent through a
byte/word swap block that is controlled by the GXB megafunction. The
data is then passed to the pattern detector to determine the start of the
data packet. When the pattern detector has detected the synchronization
pattern twice, it sets the data valid signal and starts passing the data to
the comparator.

A second PRBS generator uses the data valid signal to start generating the
expected data values. This second data set is also sent to the comparator.
The comparator module takes the output from the pattern detector block
and compares it with the output from the receive channel PRBS. The
16-bit words are compared each clock cycle. The comparator output is