Stratix gx sfp xcvr loopback, Required hardware & software, Test setup – Altera High-Speed Development Kit, Stratix GX Edition User Manual
Page 40: Stratix gx sfp xcvr loopback –12

4–12
Quartus II Version 3.0
Altera Corporation
Stratix GX SFP XCVR Loopback
High-Speed Development Kit, Stratix GX Edition User Guide
6.
Press the start pushbutton switch (Stratix_GX_PB_0).
7.
Inject an error by pressing Stratix_GX_PB_2 (S4) once. The
Stratix GX 7-segment display (D9) shows 01 and Stratix GX LED5
illuminates.
8.
Inject two more errors by pressing S4 twice. D9 displays 03.
Stratix GX SFP
XCVR Loopback
The Stratix GX SFP XCVR loopback test design tests the SFP XCVR
signals at up to 2.488 Gbps using the provided SFP XCVR loopback cards.
Required Hardware & Software
This test requires the following hardware and software:
■
SFP XCVR loopback cards
■
ATX power supply
Test Setup
To set up the test, perform the following steps.
1.
Remove power from the board.
2.
Insert the SFP loopback cards on the board as shown in Figure 4–6.
3.
Attach the SFP loopback card (labeled J3 on the card) to the SFP
transceiver connectors at J54, J64, J45, and J38 as shown in
Figure 4–7.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)