Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 101)

Altera Corporation Quartus II Version 3.0 7–19
Diagnostic Test Details Standard Tests
The PRBS generator data goes to the LVDS transmit block, which was
created using the Altera MegaWizard Plug-In Manager. The
megafunction is configured as 2 channels running at 1,000 Mbps with a
clock rate of 125 MHz. The signals then go to the SMA connectors and
loop back to the Stratix GX device using 6 SMA cables. The total signal
path lengths between channels 0 and 1 is offset by 4.5 inches.
An LVDS receive megafunction on the Stratix GX device converts the
serial data back to parallel and generates the clock used to regulate the
receive channel logic. The received data is sent through a pattern
detector/data aligner block. When the pattern detector detects the
synchronization pattern twice, it sets the data valid signal and starts
passing the data to the comparator.
A second PRBS generator uses the data valid signal to start generating the
expected data values. This second data set is also sent to the comparator.
The compare module takes the output from the data aligner block and
compares it with the output from the receive channel PRBS. The 8-bit
words are compared each clock cycle. The comparator output is high if
the words match. The output from both receive channels is ANDed
together and stored in a single-bit match register. The output of this
register drives the match LED.
The error detection and counting blocks monitor the match and data
valid signals. If the match signal goes low while data is valid, the error
flag is set and the error counter increments. The reset button clears the
error flag and resets the counter. The error insertion pushbutton inverts
one bit in one data channel for one clock cycle, which is enough to trigger
the error detection circuit.
Stratix GX SMA XCVR
This section describes the Stratix GX SMA XCVR test. Refer to “Gigabit
Transceivers with SMA Interface (Stratix GX SMA XCVR)” on page 5–17
for information on how to perform the test.
Stratix GX SMA XCVR Test Overview
The transceiver SMA design includes all of the Gigabit XCVR interface
designs for the Stratix GX device. The SMA interface portion of the design
comprises a 4-channel Altera Gigabit transceiver block (GXB) and a
Verilog HDL block with the logic required to generate a PRBS and verify
that it was received correctly. This design requires 8 SMA cables to
complete the signal loopback.
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For more information on the operation and parameterization of the GXB
megafunction, refer to Quartus II Help.