Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 114)

7–32 Quartus II Version 3.0 Altera Corporation
Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide
The error detection and counting blocks monitor the match and data
valid signals. If the match signal goes low while data is valid, the error
flag is set and the error counter is incremented. Pressing the reset button
clears the error flag and resets the counter. The error insertion
pushbutton inverts bit 0 in a data packet word for one clock cycle, which
is enough to trigger the error detection circuit.
Stratix GX HSSDC2 XCVR
This section describes the Stratix GX HSSDC2 XCVR test. Refer to
“Gigabit Transceivers with HSSDC2 Interface (Stratix GX HSSDC2
XCVR) (GX40 Device Only)” on page 5–21 for information on how to
perform the test.
Stratix GX HSSDC2 XCVR Test Overview
The transceiver HSSDC2 design includes all of the Gigabit interface
designs for the Stratix GX device. The HSSDC2 interface consists of a
4-channel Altera GXB transmitter/receiver block and a Verilog HDL
block with the logic required to generate a PRBS and verify that it was
received correctly. This design needs 2 HSSDC2 cables to complete the
signal loopback.
f
For more information on the operation and parameterization of the GXB
megafunction, refer to Quartus II Help.
The top-level BDF lets you easily modify the system parameters as
desired to evaluate a particular system configuration. By varying the GXB
megafunction parameters, you can adjust the per channel data rate up to
3,125 Mbps. The design has a Verilog HDL wrapper to name and place all
of the pins and to provide proper termination for the signals. The
Stratix GX pushbutton switches are used to control the start and stop of
the data transmission, to insert errors, and to reset the circuit. The LEDs
indicate the start of transmission, confirm that data was received
correctly, indicate the error status, and the reset condition.
The main system clock (parallel data rate) is derived from the
156.25-MHz crystal oscillator using the GXB megafunction clock output.
The data is generated in 20-bit words per channel using a PRBS generator
with a repetition count of 31, which results in a serial data rate of
3.125 Gbps. The data is then sent to a 4 channel version of the Altera GXB
megafunction, which converts the data into gigabit serial data streams.
The megafunction uses the basic protocol option.
The HSSDC2 cables feed the serial data back to the receive inputs on the
Stratix GX device. The data is converted back into parallel by the GXB
megafunction. Because the design uses the GXB megafunction’s double