Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 116)

7–34 Quartus II Version 3.0 Altera Corporation
Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide
The transmit PRBS generator comprises 20 5-bit linear feedback shift
registers. The output is taken from the MSB of each shift register. The
initial seed value is 20’h695A7. When the enable (start) signal is high, the
generator outputs a 31-word sequence that repeats until stopped. On
reset, the seed value is initialized into all of the registers. This generator
generates the data stream that exercises the system. Each transmit
channel has its own PRBS generator.
The double word option requires synchronization of the control logic
with the GXB receive section. This design uses a 10-bit alignment pattern
(10’h1A7), which allows for the internal synchronization of the
megafunction and a status signal that is sent to the word swap block in
the control logic. Data transmission only starts when a channel has been
synchronized on a per channel basis.
The data from the PRBS generators is sent to the GXB transmit block
created using the Altera MegaWizard Plug-In Manager. The
megafunction is configured as 4 channels running at 3,125 Mbps with an
input clock rate 156.25 MHz. The signals are then sent to the HSSDC2
connectors and looped back to the Stratix GX device using 2 HSSDC2
cables. The transmit of one channel becomes the receive of the next.
The receive portion of the GXB megafunction on the Stratix GX device
converts the serial data back to parallel 20-bit words. The received data is
sent through a byte/word swap block that is controlled by the GXB
megafunction. This function is required for double-word operation
because the alignment pattern is only 10 bits. The data is then passed to
the pattern detector to determine the start of the data packet. When the
pattern detector has detected the synchronization pattern twice, it sets the
data valid signal and starts passing the data to the comparator.
A second PRBS generator uses the data valid signal to start generating the
expected data values. This second data set is also sent to the comparator.
The comparator module takes the output from the pattern detector block
and compares it with the output from the receive channel PRBS. The
20-bit words are compared each clock cycle. The comparator output is
high if the words match. The output from each receive channel
comparator is stored in a single bit match register. The output of this
register drives the match LED on a per channel basis.
The error detection and counting blocks monitor the match and data
valid signals. If the match signal goes low while data is valid, the error
flag is set and the error counter is incremented. The reset pushbutton
clears the error flag and reset the counter. The error insertion pushbutton
inverts one bit in one data channel for one clock cycle, which is enough to
trigger the error detection circuit.