Cirrus Logic CS8422 - Manual (Page 65)

DS692F2 65
CS8422
12.APPLICATIONS
12.1 Reset, Power Down, and Start-Up
When RST is low the CS8422 enters a low power mode, all internal states are reset, and the outputs are
disabled. After RST transitions from low to high the part senses the resistor value on the configuration pins
(MS_SEL and SAOF) and sets the appropriate mode of operation. After the mode has been set (approxi-
mately 4
s) the part is set to normal operation and all outputs are functional.
12.2 Power Supply, Grounding, and PCB layout
The CS8422 operates from a VA = +3.3 V and VL = +1.8 V to +5.0 V supply. These supplies may be set
independently. Follow normal supply decoupling practices, see
Figure 7 and 8 for details.
Extensive use of power and ground planes, ground plane fill in unused areas, and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as
the CS8422 to minimize inductance effects and all decoupling capacitors should be as close to the CS8422
as possible. The pin of the configuration resistors not connected to MS_SEL and SAOF should be connect-
ed as close as possible to VL or DGND.
12.3 External Receiver Components
The CS8422 AES3 receiver is designed to accept both the professional and consumer interfaces. The dig-
ital audio specifications for professional use call for a balanced receiver, using XLR connectors, with
110
 ± 20% impedance. The XLR connector on the receiver should have female pins with a male shell.
Since the receiver has a very high input impedance, a 110
 resistor should be placed across the receiver
terminals to match the line impedance, as shown in Figure 26 and Figure 27 . Although transformers are not
required by the AES specification, they are strongly recommended.
If some isolation is desired without the use of transformers, a 0.01
F capacitor should be placed in series
with each input pin (RXP[3:0] and RXN[3:0]) as shown in Figure 27 . However, if a transformer is not used,
high frequency energy could be coupled into the receiver, causing degradation in analog performance.
Figure 26 and Figure 27 show an optional (recommended) DC blocking capacitor (0.1
F to 0.47 F) in se-
ries with the cable input. This improves the robustness of the receiver, preventing the saturation of the trans-
former, or any DC current flow, if a DC voltage is present on the cable.
The circuit in Figure 28 shows the input circuit for switching between up to four single-ended signals in re-
ceiver input Mode 1 (analog sensitivity mode). If the application requires switching between a single-ended
consumer interface and a differential interface, the CS8422 must be in differential mode and the input circuit
in
Figure 29 should be used for the single ended source. Standards for the consumer interface call for an
unbalanced circuit having a receiver impedance of 75
 ±5%. The connector for the consumer interface is
an RCA phono socket.
The circuit in Figure 30 shows the input circuit for switching between up to four single-ended TTL or CMOS
signals, and should be used when the S/PDIF receiver is in Receiver Input Mode 2. If the application re-
quires switching between a CMOS or TTL source and a differential source, the CS8422 must be in differ-
ential mode and the input circuit in
Figure 31 should be used for the single-ended digital source. If the
application requires switching between a single ended source in Mode 1, and a TTL or CMOS source, the
circuit in
Figure 31 should be used for the CMOS/TTL source (no RXN connection is present in this case).
When designing systems, it is important to avoid ground loops and DC current flowing down the shield of
the cable that could result when boxes with different ground potentials are connected. Generally, it is good
practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capac-
itor to chassis ground at the receiver. However, in some cases it is advantageous to have the ground of two