Digital interface receiver, 1 aes3 and s/pdif standards, 2 receiver input multiplexer – Cirrus Logic CS8422 User Manual
Page 29: 1 hardware mode control, 2 software mode control
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CS8422
6. DIGITAL INTERFACE RECEIVER
The CS8422 includes a digital interface receiver that can receive and decode audio data according to the AES3,
IEC60958, S/PDIF, and EIJ CP1201 interface standards.
The CS8422 uses either a 4:1 single-ended or 2:1 differential input mux to select the input pin(s) that will receive
input data to be decoded. A low-jitter clock (RMCK) is recovered using a PLL, which provides the digital interface
receiver with a master clock. The decoded audio data can either be routed through the SRC for sample rate con-
version, or can be an output on one of two serial audio output ports. The channel status and Q-subcode data portion
of the user data are assembled and buffered in
Channel Status Registers (23h - 2Ch)
and
, and may be accessed through the control port in either SPI or I²C Mode.
6.1
AES3 and S/PDIF Standards
This document assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to
have current copies of the AES3, IEC60958, IEC61937, and EIJ CP1201 specifications on hand for easy
reference.
The latest AES3 standard is available from the Audio Engineering Society at
t
IEC60958/61937 standard is available from the International Electrotechnical Commission at
.
The latest EIAJ CP-1201 standard is available from the Japanese Electronics Bureau at
.
Application Note 22: Overview of Digital Audio Interface Data Structures, available at
, con-
tains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the stan-
dards.
The paper titled An Understanding and Implementation of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is available from the
AES as reprint 3518.
6.2
Receiver Input Multiplexer
The CS8422’s receiver input multiplexer allows input of data compatible with AES3, S/PDIF, IEC60958, and
EIAJ CP-1201 standards. For information about recommended receiver input circuits, see
6.2.1
Hardware Mode Control
In Hardware Mode, the receiver input multiplexer is limited to a selection between two differential inputs,
RXP0/RXN0 and RXP1/RXN1. The receiver input multiplexer will decode data present at the differential
input selected by the RX_SEL pin. See
Section 8. “Hardware Mode Control” on page 39
for more details.
Multiplexer inputs are floating when not selected. Unused inputs should be tied to AGND/DGND
6.2.2
Software Mode Control
In Software Mode, CS8422 offers either a 4:1 single-ended, or a 2:1 differential input multiplexer to ac-
commodate switching between up to four channels of AES3 or S/PDIF-compatible data input. In Single-
Ended Mode, the CS8422 can switch between four single-ended signals present at RX[3:0]. In differential
mode, the CS8422 can switch between two differential signals, present on RXP0/RXN0 and RXP1/RXN1.
Multiplexer inputs are floating when not selected. Unused inputs should be tied to AGND/DGND
In Software Mode, the receiver input multiplexer is controlled through the register described in