Figure 21.hardware mode clock routing, Figure 21, Cs8422 – Cirrus Logic CS8422 User Manual
Page 40: Figure 21. hardware mode clock routing
40
DS692F2
CS8422
RXP/RXN0
RXP/RXN1
Receiver
Clock
Recovery
(PLL)
Sam ple
Rate
Converter
Serial
Audio
Output
2
OLR CK1
OSCLK1
SDOU T1
TDM _IN1
OLR CK2
OSCLK2
SDOU T2
Serial
Audio
Output
1
2
2
R X_SEL
TX_SEL
TX
Ring O scillator
(RM C K Pull-U p)
2:1
M UX
(M C LK_O U T Pull-up)
Clock
Generator
XTI XTO
MCLK_O UT
2:1
MUX
2:1
MUX
M S_SEL
S AO F
M S_SEL
SA OF
RM CK
2:1
M UX
Figure 21. Hardware Mode Clock Routing
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