Cirrus Logic CS8422 - Manual (Page 5)

DS692F2 5
CS8422
12.4.3 Serial Copy Management System (SCMS) ......................................................................... 69
12.5 Jitter Attenuation .......................................................................................................................... 69
12.6 Jitter Tolerance ............................................................................................................................ 70
12.7 Group Delay ................................................................................................................................. 70
13. PERFORMANCE PLOTS ................................................................................................................... 71
14. PACKAGE DIMENSIONS .................................................................................................................. 80
15. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 80
16. ORDERING INFORMATION .............................................................................................................. 81
17. REFERENCES .................................................................................................................................... 81
18. REVISION HISTORY .......................................................................................................................... 82
LIST OF FIGURES
Figure 1.Non-TDM Slave Mode Timing ..................................................................................................... 19
Figure 2.TDM Slave Mode Timing ............................................................................................................ 19
Figure 3.Non-TDM Master Mode Timing ................................................................................................... 19
Figure 4.TDM Master Mode Timing .......................................................................................................... 19
Figure 5.SPI Mode Timing ........................................................................................................................ 20
Figure 6.I²C Mode Timing ......................................................................................................................... 21
Figure 7.Typical Connection Diagram, Software Mode ............................................................................. 22
Figure 8.Typical Connection Diagram, Hardware Mode ........................................................................... 23
Figure 9.Serial Audio Interface Format – I²S ............................................................................................. 26
Figure 10.Serial Audio Interface Format – Left-Justified ........................................................................... 26
Figure 11.Serial Audio Interface Format – Right-Justified (Master Mode only) ........................................ 26
Figure 12.Serial Audio Interface Format – AES3 Direct Output ................................................................ 26
Figure 13.TDM Master Mode Timing Diagram .......................................................................................... 28
Figure 14.TDM Slave Mode Timing Diagram ............................................................................................ 28
Figure 15.TDM Mode Configuration (All CS8422 outputs are slave) ........................................................ 28
Figure 16.TDM Mode Configuration (First CS8422 output is master, all others are slave) ....................... 28
Figure 17.Single-Ended Receiver Input Structure, Receiver Mode 1 ....................................................... 30
Figure 18.Differential Receiver Input Structure ......................................................................................... 31
Figure 19.C/U Data Outputs ...................................................................................................................... 36
Figure 20.Typical Connection Diagram for Crystal Circuit ........................................................................ 38
Figure 21.Hardware Mode Clock Routing ................................................................................................. 40
Figure 22.Control Port Timing in SPI Mode .............................................................................................. 43
Figure 23.Control Port Timing, I²C Slave Mode Write ............................................................................... 44
Figure 24.Control Port Timing, I²C Slave Mode Read ............................................................................... 44
Figure 25.De-Emphasis Filter Response .................................................................................................. 50
Figure 26.Professional Input Circuit – Differential Mode ........................................................................... 66
Figure 27.Transformerless Professional Input Circuit – Differential Mode ................................................ 66
Figure 28.S/PDIF MUX Input Circuit – Single-Ended ................................................................................ 66
Figure 29.Receiver Mode 1 Single-Ended Input Circuit – Differential Mode ............................................. 66
Figure 30.S/PDIF MUX Input Circuit – Digital Mode ................................................................................. 66
Figure 31.TTL/CMOS Input Circuit – Differential Mode ............................................................................ 66
Figure 32.Receiver Input Attenuation – Single-ended Input ..................................................................... 67
Figure 33.Receiver Input Attenuation – Differential Input ......................................................................... 67
Figure 34.Channel Status Data Buffer Structure ....................................................................................... 68
Figure 35.Flowchart for Reading the E Buffer ........................................................................................... 68
Figure 36.CS8422 PLL Jitter Attenuation Characteristics ......................................................................... 69
Figure 37.Jitter Tolerance Template ......................................................................................................... 70
Figure 38.Wideband FFT –
0 dBFS 1 kHz Tone, 48 kHz:48 kHz ......................................................................................................... 71
Figure 39.Wideband FFT –
0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz .................................................................................................... 71