Cirrus Logic CS8422 - Manual (Page 52)

52 DS692F2
CS8422
0000 - ILRCK = MCLK/64
0001 - ILRCK = MCLK/96
0010 - ILRCK = MCLK/128
0011 - ILRCK = MCLK/192
0100 - ILRCK = MCLK/256
0101 - ILRCK = MCLK/384
0110 - ILRCK = MCLK/512
0111 - ILRCK = MCLK/768
1000 - ILRCK = MCLK/1024
SAI_MCLK – Selects the master clock (MCLK) source for the serial audio input when set to master mode
(SIMS = 1, as shown in
“Serial Audio Input Data Format (0Bh)” on page 54 ). When set to master, ILRCK
and ISCLK are derived from the MCLK selected in this register. Note: if either serial audio output port is
sourced directly by the serial audio input port, this bit determines the master clock source for the selected
serial output port when it is in master mode.
0 - XTI-XTO
1 - RMCK
11.8 SRC Output Serial Port Clock Control (08h)
SAO_CLK[3:0] – Valid only for the serial port sourced by the SRC. Selects the serial audio input master
clock-to-OLRCK ratio when the serial audio output port is set to master mode (SOMS = 1 as shown in
“Serial
Audio Output Data Format - SDOUT1 (0Ch)” on page 55 and “Serial Audio Output Data Format - SDOUT2
(0Dh)” on page 56 ).
0000 - OLRCK = MCLK/64
0001 - OLRCK = MCLK/96
0010 - OLRCK = MCLK/128
0011 - OLRCK = MCLK/192
0100 - OLRCK = MCLK/256
0101 - OLRCK = MCLK/384
0110 - OLRCK = MCLK/512
0111 - OLRCK = MCLK/768
1000 - OLRCK = MCLK/1024
SAO_MCLK – Selects the master clock (MCLK) source for the serial audio output, sourced by the SRC,
when set to master mode (SOMS1 or SOMS 2 = 1, as shown in
“Serial Audio Output Data Format - SDOUT1
(0Ch)” on page 55 and “Serial Audio Output Data Format - SDOUT2 (0Dh)” on page 56 ). When set to mas-
ter, OLRCK and OSCLK are derived from the MCLK selected in this register.
7 6 5 4 3 2 1 0
SAO_CLK3 SAO_CLK2 SAO_CLK1 SAO_CLK0 SAO_MCLK SRC_MCLK1 SRC_MCLK0 SRC_DIV
0 1 0 0 0 0 0 0