Cirrus Logic CS8422 - Manual (Page 53)

DS692F2 53
CS8422
0 - XTI-XTO
1 - RMCK
SRC_MCLK[1:0] - Controls the master clock (MCLK) source for the sample rate converter. See “SRC Mas-
ter Clock” on page 38 for details.
00 - XTI-XTO. If XTI is connected to GND or VL and XTO is left floating, the SRC MCLK will be the internal
ring oscillator.
01 - PLL clock
10 - Internal Ring Oscillator
11 - Reserved
SRC_DIV – Divide-by-two for the SRC MCLK source. Valid only if SRC_MCLK = 00.
0 - SRC MCLK is not divided. Maximum allowable SRC MCLK frequency is 33 MHz.
1 - SRC MCLK is divided. Maximum allowable SRC MCLK frequency is 49.152 MHz.
11.9 Recovered Master Clock Ratio Control & Misc. (09h)
RMCK[3:0] – Selects the RMCK/Fsi ratio, where Fsi is the sample rate of the incoming AES3-compatible
data or ISCLK/64. Note: If a serial audio output port is in master mode and sourced directly by the AES3
receiver, then RMCK is the master clock source for the selected serial output port and RMCK[3:0] determine
the MCLK/OLRCK ratio for the selected serial output port.
0000 - RMCK = 64 x Fsi
0001 - RMCK = 96 x Fsi
0010 - RMCK = 128 x Fsi
0011 - RMCK = 192 x Fsi
0100 - RMCK = 256 x Fsi
0101 - RMCK = 384 x Fsi
0110 - RMCK = 512 x Fsi
0111 - RMCK = 768 x Fsi
1000 - RMCK = 1024 x Fsi
SRC_MUTE – When SRC_MUTE is set to ‘1’, the SRC will soft-mute when it loses lock and soft unmute
when it regains lock.
0 - Soft mute disabled
1 - Soft mute enabled
7 6 5 4 3 2 1 0
RMCK3 RMCK2 RMCK1 RMCK0 SRC_MUTE Reserved Reserved Reserved
0 0 0 0 1 — — —