Cirrus Logic CS8422 - Manual (Page 4)

4 DS692F2
CS8422
6.10.2 Software Mode Control ........................................................................................................ 35
7. SAMPLE RATE CONVERTER (SRC) .................................................................................................. 37
7.1 SRC Data Resolution and Dither ................................................................................................... 37
7.1.1 Hardware Mode Control ........................................................................................................ 37
7.1.2 Software Mode Control .......................................................................................................... 37
7.2 SRC Locking .................................................................................................................................. 37
7.3 SRC Muting .................................................................................................................................... 38
7.4 SRC Master Clock ......................................................................................................................... 38
7.4.1 Hardware Mode Control ........................................................................................................ 39
7.4.2 Software Mode Control .......................................................................................................... 39
8. HARDWARE MODE CONTROL .......................................................................................................... 39
8.1 Hardware Mode Serial Audio Port Control ..................................................................................... 41
9. SOFTWARE MODE CONTROL ........................................................................................................... 43
9.1 Control Port Description ................................................................................................................ 43
9.1.1 SPI Mode ............................................................................................................................... 43
9.1.2 I²C Mode ................................................................................................................................ 44
9.1.3 Memory Address Pointer (MAP) ............................................................................................ 44
10. REGISTER QUICK REFERENCE ...................................................................................................... 45
11. SOFTWARE REGISTER BIT DEFINITIONS ...................................................................................... 48
11.1 CS8422 I.D. and Version Register (01h) ..................................................................................... 48
11.2 Clock Control (02h) ...................................................................................................................... 48
11.3 Receiver Input Control (03h) ........................................................................................................ 49
11.4 Receiver Data Control (04h) ........................................................................................................ 49
11.5 GPO Control 1 (05h) .................................................................................................................... 51
11.6 GPO Control 2 (06h) .................................................................................................................... 51
11.7 Serial Audio Input Clock Control (07h) ........................................................................................ 51
11.8 SRC Output Serial Port Clock Control (08h) ............................................................................... 52
11.9 Recovered Master Clock Ratio Control & Misc. (09h) ................................................................ 53
11.10 Data Routing Control(0Ah) ......................................................................................................... 54
11.11 Serial Audio Input Data Format (0Bh) ....................................................................................... 54
11.12 Serial Audio Output Data Format - SDOUT1 (0Ch) ................................................................... 55
11.13 Serial Audio Output Data Format - SDOUT2 (0Dh) .................................................................. 56
11.14 Receiver Error Unmasking (0Eh) .............................................................................................. 57
11.15 Interrupt Unmasking (0Fh) ......................................................................................................... 58
11.16 Interrupt Mode (10h) .................................................................................................................. 58
11.17 Receiver Channel Status (11h) ................................................................................................. 58
11.18 Format Detect Status (12h) ........................................................................................................ 59
11.19 Receiver Error (13h) ................................................................................................................. 59
11.20 Interrupt Status (14h) ................................................................................................................ 60
11.21 PLL Status (15h) ....................................................................................................................... 61
11.22 Receiver Status (16h) ............................................................................................................... 62
11.23 Fs/XTI Ratio (17h - 18h) ........................................................................................................... 63
11.24 Q-Channel Subcode (19h - 22h) ................................................................................................ 63
11.25 Channel Status Registers (23h - 2Ch) ....................................................................................... 63
11.26 IEC61937 PC/PD Burst preamble (2Dh - 30h) .......................................................................... 64
12. APPLICATIONS ................................................................................................................................. 65
12.1 Reset, Power Down, and Start-Up ............................................................................................... 65
12.2 Power Supply, Grounding, and PCB layout ................................................................................. 65
12.3 External Receiver Components ................................................................................................... 65
12.3.1 Attenuating Input signals ..................................................................................................... 66
12.3.2 Isolating Transformer Requirements ................................................................................... 67
12.4 Channel Status Buffer Management ............................................................................................ 67
12.4.1 AES3 Channel Status (C) Bit Management ........................................................................ 67
12.4.2 Accessing the E buffer ........................................................................................................ 68