Cirrus Logic CS8422 - Manual (Page 63)

DS692F2 63
CS8422
1 - There has been at least one biphase error associated with incoming AES3 data during the input of the
last AES3 data block.
BLK_PERR - Block Parity Error. Updated on DETC boundaries
0 - There has been no parity error associated with incoming AES3 data during the input of the last AES3
data block.
1 - There has been at least one parity error associated with incoming AES3 data during the input of the
last AES3 data block.
11.23 Fs/XTI Ratio (17h - 18h)
FS_XTI[15:0] - 256*Fs/XTI, where Fs is the sample rate of incoming AES3-compatible data.
The integer part of FS_XT[15:0] is represented in bits [15:10] in register 17h, and the fractional part is rep-
resented in bits [9:0] of registers 17h and 18h; with a precision of 300 Hz in Fs and is updated approxi-
mately every 2048/(XTI frequency). Reading register 17h will cause the value of 18h to freeze until
register 18h is read.
11.24 Q-Channel Subcode (19h - 22h)
Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 19h is Q[0] while
bit 0 of address 19h is Q[7]. Similarly bit 0 of address 22h corresponds to Q[79].
11.25 Channel Status Registers (23h - 2Ch)
7 6 5 4 3 2 1 0
FS_XT15 FS_XT14 FS_XT13 FS_XT12 FS_XT11 FS_XT10 FS_XT9 FS_XT8
FS_XT7 FS_XT6 FS_XT5 FS_XT4 FS_XT3 FS_XT2 FS_XT1 FS_XT0
7 6 5 4 3 2 1 0
CONTROL CONTROL CONTROL CONTROL ADDRESS ADDRESS ADDRESS ADDRESS
TRACK TRACK TRACK TRACK TRACK TRACK TRACK TRACK
INDEX INDEX INDEX INDEX INDEX INDEX INDEX INDEX
MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE
SECOND SECOND SECOND SECOND SECOND SECOND SECOND SECOND
FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME
ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO
ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE
ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND
ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME
Address Channel Status Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
23h Channel A Status Byte 0 AC0[7] AC0[6] AC0[5] AC0[4] AC0[3] AC0[2] AC0[1] AC0[0]
24h Channel A Status Byte 1 AC1[7] AC1[6] AC1[5] AC1[4] AC1[3] AC1[2] AC1[1] AC1[0]
25h Channel A Status Byte 2 AC2[7] AC2[6] AC2[5] AC2[4] AC2[3] AC2[2] AC2[1] AC2[0]
26h Channel A Status Byte 3 AC3[7] AC3[6] AC3[5] AC3[4] AC3[3] AC3[2] AC3[1] AC3[0]
27h Channel A Status Byte 4 AC4[7] AC4[6] AC4[5] AC4[4] AC4[3] AC4[2] AC4[1] AC4[0]
28h Channel B Status Byte 0 BC0[7] BC0[6] BC0[5] BC0[4] BC0[3] BC0[2] BC0[1] BC0[0]
29h Channel B Status Byte 1 BC1[7] BC1[6] BC1[5] BC1[4] BC1[3] BC1[2] BC1[1] BC1[0]
2Ah Channel B Status Byte 2 BC2[7] BC2[6] BC2[5] BC2[4] BC2[3] BC2[2] BC2[1] BC2[0]
2Bh Channel B Status Byte 3 BC3[7] BC3[6] BC3[5] BC3[4] BC3[3] BC3[2] BC3[1] BC3[0]
2Ch Channel B Status Byte 4 BC4[7] BC4[6] BC4[5] BC4[4] BC4[3] BC4[2] BC4[1] BC4[0]