Cs8422 – Cirrus Logic CS8422 User Manual
Page 12
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DS692F2
CS8422
MCLK_OUT
13
Buffered MCLK (Output) - Buffered output of XTI clock. If a 20 k
pull-up resistor to VL is present on
this pin, the SRC MCLK source will be the PLL clock, otherwise it will be the ring oscillator.
TX_SEL
14
TX Pin MUX Selection (Input) - Used to select the AES3-compatible receiver input for pass-through
to the TX pin.
RX_SEL
15
Receiver MUX Selection (Input) - Used to select the active AES3-compatible receiver input.
RCBL
16
Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status
block. Will go high for one subframe during each Z preamble following the first detected Z preamble.
If no Z preamble is detected, output is indeterminate. See
for more detail.
C
17
Channel Status Data (Output) - Serial channel status data output from the AES3-compatible
receiver, clocked by the rising and falling edges of OLRCK2 in master mode. A 20 k
pull-up resistor
to VL must be present on this pin to put the part in Hardware Mode.
TX/U
18
Receiver MUX Pass-through/User Data (Output) - If no 20 k
pull-up resistor is present on this pin
it will output a copy of the receiver mux input selected by the TX_SEL pin. If a 20 k
pull-up resistor
to VL is present on this pin, it will output serial User data from the AES3 receiver, clocked by the rising
and falling edges of OLRCK2 in master mode.
V_REG
19
Voltage Regulator In (Input) - Regulator power supply input, nominally +3.3 V.
VD_FILT
20
Digital Voltage Regulator Out (Output) - Digital core voltage regulator output. Should be connected
to digital ground through a 10 µF capacitor. Cannot be used as an external voltage source.
DGND
21
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-
nected to a common ground area under the chip.
VL
22
Logic Power (Input) - Input/Output power supply, typically +1.8 V, +2.5 V, +3.3 V, or +5.0 V.
SDOUT2
23
Serial Audio Output 2 Data Port (Output) - Audio data serial output 2 pin.
OSCLK2
24
Serial Audio Output 2 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT2 pin.
OLRCK2
25
Serial Audio Output 2 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT2 pin.
TDM_IN
26
Serial Audio Output 1 TDM Input (Input) - Time Division Multiplexing serial audio data input.
Grounded when not used. See
“Time Division Multiplexing (TDM) Mode” on page 27
for details.
SDOUT1
27
Serial Audio Output 1 Data Port (Output) - Audio data serial output 1 pin. A 20 k
pull-up to VL
present on this pin will disable de-emphasis auto detect.
OSCLK1
28
Serial Audio Output 1 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT1 pin.
OLRCK1
29
Serial Audio Output 1 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT1 pin.
SRC_UNLOCK
30
SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See
RMCK
31
Recovered Master Clock (Output) - Recovered master clock from the PLL. Frequency is 128 x,
256 x, or 512 x Fs, where Fs is the sample rate of the incoming AES3-compatible data or ISCLK/64.
If a 20 k
pull-up to VL is present on this pin, the SDOUT1 MCLK source will be RMCK, otherwise it
will be the clock input through XTI-XTO.
RST
32
Reset (Input) - When RST is low the CS8422 enters a low power mode and all internal states are
reset. On initial power up RST must be held low until the power supply is stable and all input clocks
are stable in frequency and phase.
THERMAL PAD
-
Thermal Pad - Thermal relief pad. Should be connected to the ground plane for optimized heat dissi-
pation.
Pin Name
Pin #
Pin Description