Cirrus Logic CS8422 - Manual (Page 21)

DS692F2 21
CS8422
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE
Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF.
Notes:
17. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
Parameter Symbol Min Max Unit
SCL Clock Frequency f
scl
- 100 kHz
RST Rising Edge to Start t
irs
500 - µs
Bus Free Time Between Transmissions t
buf
4.7 - µs
Start Condition Hold Time (prior to first clock pulse) t
hdst
4.0 - µs
Clock Low time t
low
4.7 - µs
Clock High Time t
high
4.0 - µs
Setup Time for Repeated Start Condition t
sust
4.7 - µs
SDA Hold Time from SCL Falling (Note 17) t
hdd
10 - ns
SDA Setup time to SCL Rising t
sud
250 - ns
Rise Time of SCL and SDA t
rc
, t
rd
- 1000 ns
Fall Time SCL and SDA t
fc
, t
fd
- 300 ns
Setup Time for Stop Condition t
susp
4.7 - µs
Acknowledge Delay from SCL Falling t
ack
300 1000 ns
t
buf t
hdst
t
lo w
t
hdd
t
high
t
sud
Stop S ta rt
S D A
S C L
t
irs
R S T
t
hdst
t
rc
t
fc
t sust
t susp
S ta rt Stop
R e p e ate d
t
rd
t
fd
t
ack
Figure 6. I²C Mode Timing