Cirrus Logic CS8422 - Manual (Page 60)

60 DS692F2
CS8422
interrupt mode is set to level active and the error source is still true. Bits that are masked off in the receiver
error mask register will always be 0 in this register.
QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries
0 - No error.
1 - Error.
CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid only
in Pro mode.
0 - No error.
1 - Error.
UNLOCK - Receiver lock status when sourced by incoming AES3-compatible data. Updated on CS block
boundaries.
0 - Receiver locked.
1 - Receiver out of lock.
V - Received AES3 Validity bit status. Updated on sub-frame boundaries.
0 - Data is valid and is normally linear coded PCM audio.
1 - Data is invalid, or may be valid compressed audio.
CONF - Confidence bit. Updated on sub-frame boundaries.
0 - No error.
1 - Confidence error. The input data stream may be near error condition due to jitter degradation.
BIP - Bi-phase error bit. Updated on sub-frame boundaries.
0 - No error.
1 - Bi-phase error. This indicates an error in the received bi-phase coding.
PAR - Parity bit. Updated on sub-frame boundaries.
0 - No error.
1 - Parity error.
11.20 Interrupt Status (14h)
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since
the register was last read. A “0” means the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be “0” in this register.
PCCH – PC burst preamble change.
7 6 5 4 3 2 1 0
PCCH OSLIP DETC CCH RERR QCH FCH SRC_UNLOCK