Cirrus Logic CS8422 - Manual (Page 33)

DS692F2 33
CS8422
The error bits are “sticky”, meaning that they are set on the first occurrence of the associated error and
will remain set until the user reads the register through the control port. This enables the register to log all
unmasked errors that occurred since the last time the register was read.
As a result of the bits “stickiness”, it is necessary to perform two reads on these registers to see if the error
condition still exists.
The Receiver Error Mask register (0Eh) allows masking of individual errors. The bits in this register default
to 00h and serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to
1, the error is unmasked, which implies the following: its occurrence will be reported in the receiver error
register, induce a pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio
sample according to the status of the HOLD bits. The exceptions are the QCRC and CCRC errors, which
do not affect the current audio sample, even if unmasked.
The HOLD bits allow a choice of the following:
– Holding the previous sample
– Replacing the current sample with zero (mute)
– Not changing the current audio sample
If needed, the current receiver error status can be output to a GPO pin in software mode, see Section
11.6 . The receiver error (RERR) and non-validity receiver error (NVERR) signals output to the GPO pins
are level active; therefore they are active only while an unmasked receiver error (register 0Eh) is occur-
ring. Reading the receiver status register (13h) does not affect the RERR/NVERR signals output to the
GPO pins. The difference between the RERR and NVERR signals on the GPO pins is that the NVERR
signal is not active while an unmasked validity bit error is occurring
For more details, refer to “Receiver Error Unmasking (0Eh)” on page 57 , “Interrupt Unmasking (0Fh)” on
page 58 , “Interrupt Mode (10h)” on page 58 , “Receiver Error (13h)” on page 59 , and “Interrupt Status
(14h)” on page 60 .
6.6.2 Hardware Mode Control
In Hardware Mode, the user may choose to output either the Non-Validity Receiver Error (NVERR) or the
Receiver Error (RERR) on the NV/RERR pin. By default the pin will output the NRERR signal. If upon star-
tup a 20 k
resistor is connected between the pin and VL, the NV/RERR pin will output the RERR error
signal. Both RERR and NVERR are updated on AES3 subframe boundaries. See “Hardware Mode Con-
trol” on page 39 for more details.
NVERR – The previous audio sample is held and passed to the serial audio output port if a parity, bi-
phase, confidence or PLL lock error occurs during the current sample or if a Q-subcode data or channel
status block CRC error occurs.
RERR – The previous audio sample is held and passed to the serial audio output port if the validity bit is
high, or a parity, bi-phase, confidence or PLL lock error occurs during the current sample or if a Q-subcode
data or channel status block CRC error occurs.
6.7 Non-Audio Detection
An AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in-
coming AES3 data stream is digital audio or not. This information is typically conveyed in channel status bit
1, which is extracted automatically by the CS8422. However, certain non-audio sources, such as AC-3
®
or
MPEG encoders, may not adhere to this convention and the bit may not be properly set. The CS8422 AES3
receiver can detect such non-audio data through the use of an auto-detect module. The auto-detect module
is similar to auto-detect software used in Cirrus Logic DSPs.