Cirrus Logic CS8422 - Manual (Page 34)

34 DS692F2
CS8422
If the AES3 stream contains sync codes in the proper format for IEC61937 or DTS ® data transmission, an
internal AUTODETECT signal will be asserted. If the sync codes no longer appear after a certain amount
of time, auto-detection will time-out and AUTODETECT will be de-asserted until another format is detected.
The AUDIO signal is the logical OR of AUTODETECT and the received channel status bit 1.
In Software Mode AUDIO is available through the GPO pins. If non-audio data is detected, the data is still
processed exactly as if it were normal audio. The exception is the use of de-emphasis auto-select feature
which will bypass the de-emphasis filter if the input stream is detected to be non-audio. It is up to the user
to mute the outputs as required.
6.7.1 Hardware Mode Control
In Hardware Mode, AUDIO is output on the V/AUDIO pin when a 20 k
 resistor is connected from the
V/AUDIO pin to VL.
6.7.2 Software Mode Control
In Software Mode, the AUDIO signal is available through the GPO pins. See “GPO Control 1 (05h)” on
page 51 for more details.
6.8 Format Detection (Software Mode Only)
In Software Mode, the CS8422 can automatically detect various serial audio input formats. The Format De-
tect Status register (12h) is used to indicate a detected format. The register will indicate if uncompressed
PCM data, IEC61937 data, DTS_LD data, DTS_CD data, or digital silence was detected. Additionally, the
IEC61937 Pc/Pd burst preambles are available in registers 2Dh-30h. See the register descriptions for more
information.
6.9 Interrupts (Software Mode Only)
The INT signal, available in Software Mode, indicates when an interrupt condition has occurred and may be
output on one of the GPOs. It can be set through bits INT[1:0] in the Control1 register (02h) to be active low,
active high, or open-drain active low. This last mode is used for active low, wired-OR hook-ups, with multiple
peripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each source
may be masked off through mask register bits. In addition, some sources may be set to rising edge, falling
edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the mi-
crocontroller, many different configurations are possible, depending on the needs of the equipment design-
er. Refer to the register descriptions for the Interrupt Unmasking (0Fh), Interrupt Mode (10h), and Interrupt
Status (14h) registers
6.10 Channel Status and User Data Handling
“Channel Status Buffer Management” on page 67 describes the overall handling of Channel Status and
User data.
6.10.1 Hardware Mode Control
In Hardware Mode, Received Channel Status (C), and User (U) bits are output on the C and TX/U pins
(U data output must be selected on the TX/U pin, see
“Hardware Mode Control” on page 39 for details).
OLRCK2 and RCBL are made available to qualify the C and U data output. Figure 19 illustrates timing of
the C and U data and their related signals.