5 register description – Rainbow Electronics AT86RF231 User Manual
Page 118
118
8111A–AVR–05/08
AT86RF231
Note
• During reset procedure, see
Section 7.1.2.8 “RESET State” on page 37
, register bits
CLKM_CTRL are shadowed. Although the clock setting of CLKM remains after reset, a read
access to register bits CLKM_CTRL delivers the reset value 1. For that reason it is
recommended to write the previous configuration (before reset) to register bits CLKM_CTRL
to align the radio transceiver behavior and register configuration. Otherwise the CLKM clock
rate is set back to the reset value (1 MHz) after the next SLEEP cycle.
For example, if the CLKM clock rate is configured to 16 MHz the CLKM clock rate remains at 16
MHz after a reset, however the register bits CLKM_CTRL are set back to 1. Since
CLKM_SHA_SEL reset value is 1, the CLKM clock rate changes to 1 MHz after the next SLEEP
cycle if the CLKM_CTRL setting is not updated.
9.6.5
Register Description
Register 0x03 (TRX_CTRL_0):
The TRX_CTRL_0 register controls the drive current of the digital output pads and the CLKM
clock rate. It is recommended to use the lowest value for the drive current to reduce the current
consumption and the emission of signal harmonics.
• Bit [7:6] - PAD_IO
Section 1.3 “Digital Pins” on page 7
.
• Bit [5:6] - PAD_IO_CLKM
These register bits set the output driver current of pin CLKM. It is recommended to reduce the
current capability to PAD_IO_CLKM = 0 (2 mA) if possible. This reduces power consumption
and spurious emissions.
Bit
7
6
5
4
3
2
1
0
+0x03
PAD_IO
PAD_IO_CLKM
CLKM_SHA_SEL
CLKM_CTRL
TRX_CTRL_0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
1
1
0
0
1
Table 9-12.
CLKM Driver Strength
Register Bit
Value
Description
PAD_IO_CLKM
0
2 mA
1
4 mA
2
6 mA
3
8 mA