Toshiba H1 SERIES TLCS-900 - Manual (Page 18)

TMP92CM22
2007-02-16 92CM22-16
3.3.3 System Clock Controller
The system clock controller generates the system clock signal (f
SYS
) for the CPU core and
internal I/O. It is used as input that fc outputted from high-frequency oscillation circuit and
PLL (Clock doubler) SYSCR1, SYSCR1 sets the high-frequency
clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16). These functions can reduce
the power consumption of the equipment in which the device is installed.
Single clock mode is set by resetting, initialized to = “100”. This setting will
cause the system clock (f
SYS
) to be set to fc/32 (fc/16 ×1/2).
For example, f
SYS
is set to 1.25 MHz when the 40MHz oscillator is connected to the X1
and X2 pins.
(1) Clock gear controller
f
FPH
is set according to the contents of the clock gear select register
SYSCR1 to either fc, fc/2, fc/4, fc/8, or fc/16. Using the clock gear to select a
lower value of f
FPH
reduces power consumption.
Example:
Changing to a high-frequency gear
SYSCR1 EQU 10E1H
LD (SYSCR1), XXXX0100B ; Changes system clock f
SYS
to fc/32.
X: Don’t care
(High-speed clock gear changing)
To change the clock gear, write the register value to the SYSCR1
register. It is necessary the warm-up time until changing after writing the register
value.
There is the possibility that the instruction next to the clock gear changing
instruction is executed by the clock gear before changing. To execute the instruction
next to the clock gear switching instruction by the clock gear after changing, input the
dummy instruction as follows (Instruction to execute the write cycle).
Example:
SYSCR1 EQU 10E1H
LD (SYSCR1), XXXX0001B ; Changes f
SYS
to fc/4.
LD (DUMMY), 00H ; Dummy instruction.
Instruction to be executed
after clock gear has changed.