Toshiba H1 SERIES TLCS-900 - Manual (Page 146)

TMP92CM22
2007-02-16 92CM22-144
Figure 3.9.3 Block Diagram of SIO1
Selector
φT0
φT2
φT8
φT32
SC1MOD0
Receive buffer 1 (Shift register)
RXDCLK
SC1MOD0
Pr
escaler
Selector
TA0TRG
(from TMRA0)
UART
mode
BR1CR
Baud rate generater
Selector
SC1MOD0
Selector
÷ 2
I/O interface mode
SC1CR
Receive control
(UART only
÷ 16)
Transmission
counter
(UART only
÷ 16)
Receive buffer
Transmission
control
INTRX1
INTTX1
Receive buffer 2 (SC1BUF) RB8 Error flag
SC1CR
Serial channel
interrupt control
TB8
CTS1
(Shared
with PF5)
TXD1
(Shared
with PF3)
Transmission buffer
(SC1BUF)
RXD1
(Shared
with PF4)
TXDCLK
SC1MOD0
f
io
SC1MOD0
SCLK1 output
(Shared
with PF5)
SCLK1 input
(Shared
with PF5)
SIOCLK
Internal data bus
Parity control
SC1CR
Serial clock generation circuit
BR1CR
BR1ADD
BR1CR
I/O interface mode
φT0
2 64 4 8 16 32
Prescaler
φT2 φT8 φT32
Interrupt request