Toshiba H1 SERIES TLCS-900 - Manual (Page 124)

TMP92CM22
2007-02-16 92CM22-122
Figure 3.8.2 Block Diagram of TMRB1
Ti
mer
flip-
flop
control
Match detection
Match detection
32
16
8
4
2
φT1
φT4
φT16
Run/ clear
φT1 φT4
φT16
TB1MOD
Pr
escaler
clock:
φT0
External interrupt input
INT4 INT5
Selecto
r
Register buffer
1
2
TB1RUN<
TB1R
UN>
TB1MOD
TB0FF
0
Internal data bus
TB1RUN
TB1RUN
Intenal data bus
TB1MO
D
Register 1 INTTB01
TB0FF
1
TB1OUT0 TB1OUT1
16-bit timer regis
ter
TB1REG0H/L
16-bit comparato
r
(CP12)
16-bit timer regis
ter
TB1R
G1H/L
16-bit comparato
r (CP13
)
TB1MO
D
Internal data bus
Internal data bus
Register 0 INTTB00
Ti
mer fl
ip
-fl
op
output
Ti
me
r
flip-
flop
Overflow interrupt INTTB
OF0
Capture register 0
TB1CP0H/L
Caputure registe
r
1
TB1CP1H/L
TA1O
UT
TB1IN0 TB1IN1
(from
TMRA23
)
16-bit up counter
(UC1)
Count clock
Interrup
t output
Capture,
external interrupt
control