10 subsystem identification register, 11 capabilities pointer register, 12 interrupt line register – Texas Instruments Dual/Single Socket CardBus and UntraMedia Controller PCI7621 User Manual
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12.10 Subsystem Identification Register
The subsystem identification register, used for system and option card identification purposes, may be required for
certain operating systems. This read-only register is initialized through the EEPROM and can be written through the
subsystem access register at PCI offset 8Ch (see Section 12.23). All bits in this register are reset by GRST only.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Subsystem identification
Type
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Subsystem identification
Offset:
2Eh
Type:
Read/Update
Default:
0000h
12.11 Capabilities Pointer Register
The power management capabilities pointer register provides a pointer into the PCI configuration header where the
power-management register block resides. Since the PCI power management registers begin at 80h, this read-only
register is hardwired to 80h.
Bit
7
6
5
4
3
2
1
0
Name
Capabilities pointer
Type
R
R
R
R
R
R
R
R
Default
1
0
0
0
0
0
0
0
Register:
Capabilities pointer
Offset:
34h
Type:
Read-only
Default:
80h
12.12 Interrupt Line Register
The interrupt line register is programmed by the system and indicates to the software which interrupt line the SD host
controller has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been
assigned to the function.
Bit
7
6
5
4
3
2
1
0
Name
Interrupt line
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
Register:
Interrupt line
Offset:
3Ch
Type:
Read/Write
Default:
FFh