Texas Instruments Dual/Single Socket CardBus and UntraMedia Controller PCI7621 - Manual (Page 166)

7−6
7.7 Header Type and BIST Register
The header type and built-in self-test (BIST) register indicates the PCI7x21/PCI7x11 PCI header type and no built-in
self-test. See Table 7−6 for a complete description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Header type and BIST
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Register: Header type and BIST
Offset: 0Eh
Type: Read-only
Default: 0080h
Table 7−6. Header Type and BIST Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 BIST R
Built-in self-test. The PCI7x21/PCI7x11 controller does not include a BIST; therefore, this field returns
00h when read.
7−0 HEADER_TYPE R
PCI header type. The PCI7x21/PCI7x11 controller includes the standard PCI header, which is
communicated by returning 80h when this field is read.
7.8 OHCI Base Address Register
The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control.
When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of
memory address space are required for the OHCI registers. See Table 7−7 for a complete description of the register
contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OHCI base address
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OHCI base address
Type RW RW RW RW RW R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: OHCI base address
Offset: 10h
Type: Read/Write, Read-only
Default: 0000 0000h
Table 7−7. OHCI Base Address Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−11 OHCIREG_PTR RW
OHCI register pointer. This field specifies the upper 21 bits of the 32-bit OHCI base address register.
The default value for this field is all 0s.
10−4 OHCI_SZ R
OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a
2K-byte region of memory.
3 OHCI_PF R
OHCI register prefetch. Bit 3 returns 0 when read, indicating that the OHCI registers are
nonprefetchable.
2−1 OHCI_MEMTYPE R
OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register
is 32 bits wide and mapping can be done anywhere in the 32-bit memory space.
0 OHCI_MEM R
OHCI memory indicator. Bit 0 returns 0 when read, indicating that the OHCI registers are mapped
into system memory space.