Pgsr0 bit definitions -32, Pgsr1 bit definitions -32, Table 3-16 – Intel PXA255 User Manual
Page 94: Table 3-17
3-32
Intel® PXA255 Processor Developer’s Manual
Clocks and Power Manager
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-16. PGSR0 Bit Definitions
0x40F0_0020
PGSR0
Clocks and Power Manager
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SS
3
1
SS
3
0
SS
2
9
SS
2
8
SS
2
7
SS
2
6
SS
2
5
SS
2
4
SS
2
3
SS
2
2
SS
2
1
SS
2
0
SS
1
9
SS
1
8
SS
1
7
SS
1
6
SS
1
5
SS
1
4
SS
1
3
SS
1
2
SS
1
1
SS
1
0
SS9
SS8
SS7
SS6
SS5
SS4
SS3
SS2
SS1
SS0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
[31:0]
SSx
If programmed as an output, Sleep state of GPx
0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
Table 3-17. PGSR1 Bit Definitions
0x40F0_0024
PGSR1
Clocks and Power Manager
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SS
6
3
SS
6
2
SS
6
1
SS
6
0
SS
5
9
SS
5
8
SS
5
7
SS
5
6
SS
5
5
SS
5
4
SS
5
3
SS
5
2
SS
5
1
SS
5
0
SS
4
9
SS
4
8
SS
4
7
SS
4
6
SS
4
5
SS
4
4
SS
4
3
SS
4
2
SS
4
1
SS
4
0
SS
3
9
SS
3
8
SS
3
7
SS
3
6
SS
3
5
SS
3
4
SS
3
3
SS
3
2
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
[31:0]
SSx
If programmed as an output, Sleep state of GPx
0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.