Intel PXA255 - Manual (Page 289)

Intel® PXA255 Processor Developer’s Manual 7-27
LCD Controller
In passive mode, EFW must be set to zero so that no EOF wait states are generated. Use VSW
exclusively in passive mode to insert line clock wait states, which allow the LCD controller’s
DMAC to fill the palette and insert additional pixels before the start of the next frame.
Vertical Sync Pulse Width (VSW) — used to specify the pulse width of the vertical
synchronization pulse in active mode or to add extra “dummy” line clock wait states between the
end and beginning of frame in passive mode.
In active mode (LCCR0[PAS]=1), L_FCLK is used to generate the vertical sync signal and is
asserted each time the last line or row of pixels for a frame is sent to the display and a
programmable number of line clock wait states as specified by LCCR1[BLW] have elapsed. When
L_FCLK is asserted, the value in VSW is transferred to a 6-bit down counter, which uses the line
clock frequency to decrement. When the counter reaches zero, L_FCLK is negated. VSW can be
programmed to generate a vertical sync pulse width ranging from 1 to 64 line clock periods. VSW
must be programmed with the desired number of line clocks minus one. The polarity (active and
inactive state) of the L_FCLK pin is programmed using the vertical sync polarity (VSP) bit in
LCCR3.
In passive mode (LCCR0[PAS]=0), VSW does not affect the timing of the L_FCLK pin, but rather
can be used to add extra line clock wait states between the end of each frame and the beginning of
the next frame. When the last line clock of a frame is negated, the value in VSW is transferred to a
6-bit down counter that uses the line clock frequency to decrement. When the counter reaches zero,
the next frame begins. VSW can be programmed to generate from 1 to 64 dummy line clock
periods between each frame in passive mode. VSW must be programmed to allow:
• enough wait states to occur between frames such that the LCD’s DMAC is able to fully load
the on-chip palette (if applicable)
• a sufficient number of encoded pixel values to be fetched from the frame buffer, to be
processed by the dither logic and placed in the output FIFO, ready to be sent to the LCD data
pins.
The number of wait states required is system dependent, depending on such factors as:
• palette buffer size (none; 8, 32 or 512 bytes)
• memory system speed (number of wait states, burst speed, number of beats)
• Palette DMA request delay, LCCR0[PDD].
The line clock pin does toggle during the insertion of the line clock wait state periods.
VSW does not affect generation of the frame clock signal in passive mode. Passive LCD displays
require that the frame clock be active on the rising edge of the first line clock pulse of each frame,
with adequate setup and hold time. To meet this requirement, the LCD controller’s frame clock pin
is asserted on the rising edge of the first pixel clock for each frame. The frame clock remains
asserted for the remainder of the first line as pixels are sent to the display. It is then negated on the
rising edge of the first pixel clock of the second line of each frame.
Lines Per Panel (LPP) — specifies the number of lines or rows present on the LCD panel being
controlled. In single-panel mode, it represents the total number of lines for the entire LCD display.
LPP is used to count the correct number of line clocks that must occur before the frame clock can
be pulsed. In dual-panel mode, it represents half the number of lines of the entire LCD display,
which is split into two panels. LPP is a 10-bit value that represents between 1 and 1024 lines per
screen. It must be programmed with the actual height of the display minus one. It is recommended
not to exceed 480 pixels. For portrait mode panels, more than 480 pixels can be used as long as
total pixels do not exceed 480,000. For example, a 480x640 portrait mode panel can be used.