Intel PXA255 User Manual
Page 4

iv
Intel® PXA255 Processor Developer’s Manual
Contents
95.85 MHz Peripheral Phase Locked Loop ..........................................................3-5
147.46 MHz Peripheral Phase Locked Loop ........................................................3-5
Power Manager Registers ...............................................................................................3-22
3.5.1
Power Manager Control Register (PMCR) .........................................................3-23
Power Manager General Configuration Register (PCFR)...................................3-24
Power Manager Wake-Up Enable Register (PWER)..........................................3-25
Power Manager Rising-Edge Detect Enable Register (PRER) ..........................3-26
Power Manager Falling-Edge Detect Enable Register (PFER) ..........................3-27
Power Manager GPIO Edge Detect Status Register (PEDR).............................3-28
Power Manager Sleep Status Register (PSSR) .................................................3-29
Power Manager Scratch Pad Register (PSPR) ..................................................3-30
Power Manager Fast Sleep Walk-up Configuration Register (PMFW) ...............3-31
3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2).........3-31
3.5.11 Reset Controller Status Register (RCSR)...........................................................3-33
Core Clock Configuration Register (CCCR) .......................................................3-34
Coprocessor 14: Clock and Power Management ............................................................3-38
3.7.1
Core Clock Configuration Register (CCLKCFG).................................................3-39
Power Mode Register (PWRMODE)...................................................................3-40
Driving the Crystal Pins from an External Clock Source.....................................3-41
Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator...............3-41