Intel PXA255 - Manual (Page 511)

Intel® PXA255 Processor Developer’s Manual 15-9
MultiMediaCard Controller
15.2.7 Clock Control
Both the MMC controller and the software can control the MMC bus clock (MMCLK) by turning
it on and off. This helps to control the data flow to prevent under runs and overflows and also
conserves power. The software can also change the frequency at any time to achieve the maximum
data transfer rate specified for a card’s identification frequency.
The MMC controller has an internal frequency generator that may start, stop, and divide the MMC
bus clock. The software may start and stop the clock by setting the appropriate bits in the
MMC_STRPCL register. The MMCLK frequency is controlled by the value written in the
MMC_CLKRT register.
To write any MMC controller register for the next command sequence, software must:
1. Stop the clock.
2. Write the registers.
3. Restart the clock.
Software must not stop the clock when it attempts to read the receive FIFOs or write the transmit
FIFOs. When the clock stops, it resets the pointers in the FIFOs and any data left in the FIFOs can
not be transmitted or accessed. When the receive FIFOs are empty and the
MMC_STAT[DATA_TRAN_DONE] is set, software may stop the clock.
The software can specify the clock divisor of the 20 Mhz clock by setting the MMC_CLKRT
register. The clock rate may be set as:
• 20 Mhz
• 1/2 of 20 Mhz, 10 Mhz
• 1/4 of 20 Mhz, 5 Mhz
• 1/8 of 20 Mhz, 2.5 Mhz
• 1/16 of 20 Mhz, 1.25 Mhz
• 1/32 of 20 Mhz, 625 khz
• 1/64 if 20 Mhz, 312.5 khz
The controller can also turn the clock off automatically. If both receive FIFOs become full during
data reads, or one receive FIFO is being read by the software and the other receive FIFO becomes
full, or both transmit FIFOs become empty during data writes, or one transmit FIFO is being
written by the software and the other transmit FIFO is empty, the controller will automatically turn
the clock off to prevent data overflows and under runs. For read data transfers, the controller turns
the clock back on after a receive FIFO has been emptied. For write data transfers, the controller
turns the clock back on after the transmit FIFO is no longer empty.
Warning: Stopping the clock while data is in the transmit or receive FIFOs will cause unpredictable results.
If the software stops the clock at any time, it must wait for the MMC_STAT[CLK_EN] status bit to
be cleared before proceeding.