Intel PXA255 - Manual (Page 79)

Intel® PXA255 Processor Developer’s Manual 3-17
Clocks and Power Manager
If the external voltage regulator is failing or the main battery is low or missing, some systems must
enter sleep mode quickly. When nBATT_FAULT or nVDD_FAULT is asserted, the system is
required to shut down immediately.
To allow the assertion of nVDD_FAULT or nBATT_FAULT to cause an imprecise data abort, set
the Imprecise Data Abort Enable (IDAE) bit in the PMCR. Setting the IDAE bit in the PMCR will
result in software executing the data abort handler routine as part of entering sleep mode. If the
IDAE bit is clear, the processor enters sleep mode immediately without executing the abort handler
routine.
Note: Using an exception handler to invoke sleep in response to a power fault event is advantageous
because software can clear the PMFW[FWAKE] bit and configure the power management IC to
use PWR_EN to disable the core power supply during sleep to minimize power consumption from
a critically low battery.
PSSR[VFS] and PSSR[BFS] can not be used prior to entering Sleep Mode to determine which type
of fault occurred, VDD fault or battery fault, respectively. If either nVDD_FAULT or
nBATT_FAULT signals are asserted or if both are asserted at the same time (and the IDAE bit of
the PMCR is set), the software data abort handler will be called. Since there is only one common
data abort handler, software must first determine if one of the two nVDD_FAULT or
nBATT_FAULT assertion events resulted in an imprecise data abort by reading Coprocessor 7,
Register 4, Bit 5 (PSFS). If the PSFS bit is cleared, neither a nVDD_FAULT or nBATT_FAULT
assertion occurred and the data abort handler was called for some other reason. If the PSFS bit is
set, this indicates either a nVDD_FAULT or nBATT_FAULT assertion occurred, but it is not
possible to determine which of the two faults was asserted. For either case, nVDD_FAULT or
nBATT_FAULT assertion, software should shut the system down as quickly as possible by
performing the steps outlined below to enter Sleep Mode.
Note: All addresses (data and instruction) used in the abort handler routines should be resident and
accessible in the memory page tables, i.e. system software developers should ensure no further
aborts occur while executing an abort handler. The processor does not support recursive (nested)
aborts. The system must not assert nBATT_FAULT or nVDD_FAULT signals more than once
before nRESET_OUT is asserted. System software can not return to normal execution following a
nBATT_FAULT or nVDD_FAULT. If a battery or VDD fault occurs while executing in the abort
mode, the abort handler is reentered. This condition of a recursive abort occurrence can be detected
in software by reading the Saved Program Status Register (SPSR) to see if the previous context
was executing in abort mode.
To enter Sleep Mode, software must complete the following sequence:
1. Software uses external memory and the Power Manager Scratch Pad Register (PSPR) to
preserve critical states.
2. Software sets Sleep Mode in PWRMODE[M]. An interrupt immediately aborts Sleep Mode
and normal processing resumes.
3. The CPU waits until all instructions in the pipeline are complete.
4. The Memory Controller completes outstanding transactions in its buffers and from the CPU.
New transactions from the LCD or DMA controllers are ignored.
5. The Memory Controller places the SDRAM in self-refresh mode.
6. The Power Manager switches the GPIO output pins to their sleep state. This sleep state is
programmed in advance by loading the Power Manager GPIO Sleep State registers (PGSR0,
PGSR1, and PGSR2). To avoid contention on the bus when the processor attempts to wake up,
ensure that the chip selects are not set to 0 during sleep mode.