Intel PXA255 - Manual (Page 66)

3-4 Intel® PXA255 Processor Developer’s Manual
Clocks and Power Manager
3.3.1 32.768 kHz Oscillator
The 32.768 kHz oscillator is a low power, low frequency oscillator that clocks the RTC and Power
Manager. This oscillator is disabled out of Hardware Reset and the RTC and Power Manager
blocks use the 3.6864 MHz oscillator instead. Software writes the Oscillator On bit in the
Oscillator Configuration Register to enable the 32.768 kHz.This configures the RTC and Power
Manager to use the 32.768 kHz oscillator after it stabilizes.
32.768 kHz oscillator use is optional and provides the lowest power consumption during Sleep
Mode. In less power-sensitive applications, disable the 32.768 kHz oscillator in the Oscillator
Configuration Register (OSCC) and leave the external pins floating (no external crystal required)
for cost savings. If the 32.768 kHz oscillator is not in the system, the frequency of the RTC and
Power Manager will be 3.6864 MHz divided by 112 (32.914 kHz). In Sleep, the 3.6864 MHz
oscillator consumes hundreds of microamps of extra power when it stays enabled. See
Section 3.5.2, “Power Manager General Configuration Register (PCFR)” on page 3-24 for
information on The Oscillator Power Down Enable (OPDE) bit, which determines if the
3.6864 MHz oscillator is enabled in Sleep Mode. No external capacitors are required.
3.3.2 3.6864 MHz Oscillator
The 3.6864 MHz oscillator provides the primary clock source for the processor. The on-chip PLL
frequency multipliers, Synchronous Serial Port (SSP), Pulse Width Modulator (PWM), and the
Operating System Timer (OST) use the 3.6864 MHz oscillator as a reference. Out of Hardware
Reset, the 3.6864 MHz oscillator also drives the RTC and Power Manager (PM). The user may
then enable the 32.768 kHz oscillator, which will drive the RTC and PM after it is stabilized. The
3.6864 MHz oscillator can be disabled during Sleep Mode by setting the OPDE (see
Section 3.5.2 )
bit but only if the 32.768 kHz oscillator is enabled and stabilized (both the OON and OOK bits in
the OSCC set). See
Section 3.6.3 for more information. No external capacitors are required.
3.3.3 Core Phase Locked Loop
The Core PLL is the clock source of the CPU Core, the Memory Controller, the LCD Controller,
and DMA Controller. The Core PLL uses the 3.6864 MHz oscillator as a reference and multiplies
its frequency by the following variables:
• L: Crystal Frequency to Memory Frequency Multiplier, set to 27, 32, 36, 40, or 45.
• M: Memory Frequency to Run Mode Frequency Multiplier, set to 1 or 2.
• N: Run Mode Frequency to Turbo Mode Frequency Multiplier, set to 1.0, 1.5, 2.0, or 3.0.
The output frequency selections are shown in Table 3-1, “Core PLL Output Frequencies for
3.6864 MHz Crystal” . See Section 3.6.1 for programming information on the L, M, and N factors.
See Section 3.6.1, “Core Clock Configuration Register (CCCR)” for the hexadecimal settings.
Do not choose a combination that generates a frequency that is not supported in the voltage range
and package in which the processor is operating.
SDCLK must not be greater than 100 MHz. If MEMCLK is greater than 100 MHz, the SDCLK to
MEMCLK ratio must be set to 1:2 in the Memory Controller.