Intel PXA255 - Manual (Page 38)

2-8 Intel® PXA255 Processor Developer’s Manual
System Architecture
2.9 Power on Reset and Boot Operation
Before the device that uses the processor is powered on, the system must assert nRESET and
nTRST. To allow the internal clocks to stabilize, all power supplies must be stable for a specified
period before nRESET or nTRST are deasserted. When nRESET is asserted, nRESET_OUT is
driven active and can be used to reset other devices in the system. For additional information, see
the Intel® PXA255 Processor Design Guide.
When the system deasserts nRESET and nTRST, the processor deasserts nRESET_OUT a
specified time later and the device attempts to boot from physical address location 0x0000_0000.
The BOOT_SEL[2:0] pins are sampled when reset is deasserted and let the user specify the type
and width of memory device from which the processor attempts to boot. The software can read the
pins as described in
Section 6.10.2, “Boot Time Defaults” on page 6-72 .
2.10 Power Management
The processor offers a number of modes to manage power in the system. These range widely in
level of power savings and level of functionality. The following modes are supported:
• Turbo Mode: low latency (nanoseconds) switch between two preprogrammed frequencies.
• Run Mode: normal full function mode.
• Idle Mode: core clocks are stopped - resume through an interrupt.
• Sleep Mode: low power mode that does not save state but keeps I/Os powered. The RTC,
Power Manager, and Clock modules are saved, except for Coprocessor 14.
Note: In low power modes, ensure that input pins are not floating and output pins are not driven by an
external device that opposes how the processor is driving that pin. In either case, the system will
draw excess current. Current draw that varies in sleep mode or varies greatly between parts is
typically a sign of floating pins.
Section 3.4, “Resets and Power Modes” describes the modes in detail.
2.11 Pin List
Some of the processor pins can be connected to multiple signals. The signal connected to the pin is
determined by the GPIO Alternate Function Select Registers (GAFRn m). Some signals can go to
multiple pins. The signal must be routed to only one pin by using the GAFRn m registers. Because
this is true, some pins are listed twice, once in each unit that can use the pin.
Table 2-5. Processor Pin Types
Type Function
IC CMOS input
OC CMOS output
OCZ CMOS output, Hi-Z
ICOCZ CMOS bidirectional, Hi-Z