Intel PXA255 - Manual (Page 423)

Intel® PXA255 Processor Developer’s Manual 12-23
USB Device Controller
12.6.1.2 UDC Active (UDA)
This read-only bit can be read to determine if the UDC is currently active or in a USB reset. This
bit is only valid when the UDC is enabled. A zero indicates that the UDC is currently receiving a
USB reset from the host. A one indicates that the UDC is currently involved in a transaction.
12.6.1.3 UDC Resume (RSM)
When the UDC is in a suspend state, this bit can be written to force the UDC into a non-idle state
(K state) for 3 ms to perform a remote wakeup operation. If the host PC does not start a wakeup
sequence in 3 ms, the UDC returns to the suspend mode. This bit is a trigger bit for the UDC and is
automatically cleared.
12.6.1.4 Resume Interrupt Request (RESIR)
The resume interrupt request bit is set if the SRM bit in the UDC control register is cleared, the
UDC is currently in the suspended state, and the USB is driven with resume signalling.
12.6.1.5 Suspend Interrupt Request (SUSIR)
The suspend interrupt request register is set when the USB remains idle for more than 6 ms. The
SUSIR bit retains state so software can determine that the USB is idle. If SRM is zero, SUSIR
being set will not generate an interrupt but status continues to be updated.
12.6.1.6 Suspend/Resume Interrupt Mask (SRM)
This bit masks or enables the suspend interrupt request to the interrupt controller. When SRM is 1,
the interrupt is masked and the setting of SUSIR will not generate an interrupt. When SRM is 0, the
setting of SUSIR generates an interrupt when the USB is idle for more than 6ms. Programming
SRM does not affect the state of SUSIR.
12.6.1.7 Reset Interrupt Request (RSTIR)
The reset interrupt request register is set when the host issues a reset. When the host issues a reset,
the entire UDC is reset. The RSTIR bit retains its state so software can determine that the design
was reset. If REM is zero, RSTIR being set does not generate an interrupt but status continues to be
updated.
12.6.1.8 Reset Interrupt Mask (REM)
This bit masks or enables the reset interrupt request to the interrupt controller. When REM is 1, the
interrupt is masked and the setting of RSTIR does not generate an interrupt. When REM is 0, the
RSTIR setting generates an interrupt when the USB host controller issues an UDC reset.
Programming REM does not affect the state of RSTIR.
The UDE bit is cleared to zero, which disables the UDC following a Megacell reset. Writes to
reserved bits are ignored and reads return zeros.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.