Intel PXA255 - Manual (Page 516)

15-14 Intel® PXA255 Processor Developer’s Manual
MultiMediaCard Controller
After completely reading or writing the data FIFOs, the software must wait for the appropriate
interrupts. The status register, MMC_STAT, must be read to ensure that the transaction is complete
and to check the status of the transaction.
When using DMA request signals, the controller indicates to the DMA when a FIFO is ready for
reading or writing. It is expected that all FIFO reads and writes will empty and fill the FIFO to
which it is connected. If at any time the MMC_TXFIFO is not filled (32 bytes) by the software, the
software must notify the controller by setting the MMC_PRTBUF[BUF_PART_FULL]. The
software can write more bytes of data than is needed into the MMC_TXFIFO, but the controller
will only transmit the number of bytes in the MMC_BLKLEN register.
At the end of any data transfer or busy signal on the MMC bus, the MMC controller waits eight
MMC clocks before asserting the MMC_I_REG[DATA_TRAN_DONE] interrupt to notify the
software that the data transfer is complete. This guarantees that the specified minimum of eight
MMC clocks occurs between a data transfer and the next command.
On write data transfers, a card may become busy while programming the data. The software may
wait for the card to become not busy by writing the MMC_I_MASK register and waiting for the
MMC_I_REG[PRG_DONE] interrupt or the software can start communication to another card.
Refer to The MultiMediaCard System Specification for additional information.
The MMC controller performs data transactions in all the basic modes: single block, multiple
blocks, and stream modes.
15.3.2.1 Block Data Write
In a single block data write, a block of data is written to a card. In a multiple block write, the
controller performs multiple single block write data transfers on the MMC bus.
After turning the clock on to start the command sequence, the software must program the DMA to
fill the MMC_TXFIFO (write 32 bytes). The software must continue to fill the FIFO until all of the
data has been written to the FIFOs. The software must then wait for the transmission to complete
by waiting for the MMC_I_REG[DATA_TRAN_DONE] interrupt and
MMC_I_REG[PRG_DONE] interrupt. The software can then read the status register,
MMC_STAT, to verify the status of the transaction.
For multiple block writes, The MultiMediaCard System Specification specifies that the card will
continue to receive blocks of data until the stop transmission command is received. After the
controller has transmitted the number of bytes specified in the MMC_NOB register, the controller
will stop transmitting data. After the MMC_I_REG[DATA_TRAN_DONE] interrupt is detected,
the software must setup the controller to send the stop transmission command, CMD12. Consult
The MultiMediaCard System Specification for a description of the stop transmission command.
If both transmit FIFOs become empty during data transmission, the MMC controller turns the
clock off. After a FIFO has been written, the controller turns the clock back on.
In a block data write, these parameters must be specified:
• The data transfer is a write.
• The block length if the block length is different from the previous block data transfer or this is
the first time that the parameter is being specified.
• The number of blocks to be transferred.