Intel PXA255 - Manual (Page 21)

Intel® PXA255 Processor Developer’s Manual xxi
Contents
12-24 UFNHR Bit Definitions ...........................................................................................................12-43
12-25 UFNLR Bit Definitions............................................................................................................12-44
12-26 UBCR2/4/7/9/12/14 Bit Definitions.........................................................................................12-45
12-27 UDDR0 Bit Definitions ...........................................................................................................12-46
12-28 UDDR1/6/11 Bit Definitions ...................................................................................................12-46
12-29 UDDR2/7/12 Bit Definitions ...................................................................................................12-47
12-30 UDDR3/8/13 Bit Definitions ...................................................................................................12-47
12-31 UDDR4/9/14 Bit Definitions ...................................................................................................12-48
12-32 UDDR5/10/15 Bit Definitions .................................................................................................12-48
12-33 USB Device Controller Register Summary ............................................................................12-48
13-1 External Interface to CODECs.................................................................................................13-2
13-2 Supported Data Stream Formats.............................................................................................13-3
13-3 Slot 1 Bit Definitions.................................................................................................................13-7
13-4 Slot 2 Bit Definitions.................................................................................................................13-7
13-5 Input Slot 1 Bit Definitions......................................................................................................13-10
13-6 Input Slot 2 Bit Definitions......................................................................................................13-11
13-7 GCR Bit Definitions................................................................................................................13-20
13-8 GSR Bit Definitions ................................................................................................................13-22
13-9 POCR Bit Definitions .............................................................................................................13-23
13-10 PICR Bit Definitions ...............................................................................................................13-24
13-11 POSR Bit Definitions..............................................................................................................13-25
13-12 PISR Bit Definitions ...............................................................................................................13-25
13-13 CAR Bit Definitions ................................................................................................................13-26
13-14 PCDR Bit Definitions..............................................................................................................13-26
13-15 MCCR Bit Definitions .............................................................................................................13-27
13-16 MCSR Bit Definitions .............................................................................................................13-28
13-17 MCDR Bit Definitions .............................................................................................................13-28
13-18 MOCR Bit Definitions.............................................................................................................13-29
13-19 MICR Bit Definitions...............................................................................................................13-30
13-20 MOSR Bit Definitions .............................................................................................................13-30
13-21 MISR Bit Definitions...............................................................................................................13-31
13-22 MODR Bit Definitions.............................................................................................................13-31
13-23 Address Mapping for CODEC Registers ...............................................................................13-33
13-24 Register Mapping Summary ..................................................................................................13-35
14-1 External Interface to CODEC...................................................................................................14-2
14-2 Supported Sampling Frequencies ...........................................................................................14-6
14-3 SACR0 Bit Definitions..............................................................................................................14-9
14-4 FIFO Write/Read table...........................................................................................................14-10
14-5 TFTH and RFTH Values for DMA Servicing ..........................................................................14-10
14-6 SACR1 Bit Definitions............................................................................................................14-11
14-7 SASR0 Bit Definitions ............................................................................................................14-12
14-8 SADIV Bit Definitions .............................................................................................................14-13
14-9 SAICR Bit Definitions.............................................................................................................14-13
14-10 SAIMR Bit Descriptions .........................................................................................................14-14
14-11 SADR Bit Descriptions...........................................................................................................14-14
14-12 Register Memory Map ...........................................................................................................14-16
15-1 Command Token Format.........................................................................................................15-2
15-2 MMC Data Token Format ........................................................................................................15-2
15-3 SPI Data Token Format ...........................................................................................................15-2
15-4 MMC Signal Description ..........................................................................................................15-6