Intel PXA255 - Manual (Page 311)

Intel® PXA255 Processor Developer’s Manual 8-3
Synchronous Serial Port Controller
• SSPRXD–Receive signal for inbound data, from peripheral to system.
A data frame can be configured to contain from 4 to 16 bits. Serial data is transmitted most
significant bit first.
The SSPC supports three formats: Motorola SPI, Texas Instruments SSP, and National Microwire.
The three formats have significant differences, as described below.
SSPSFRM varies for each protocol as follows:
• For SPI and Microwire formats, SSPSFRM functions as a chip select to enable the external
device (target of the transfer), and is held active-low during the data transfer.
• For SSP format, SSPSFRM is pulsed high for one serial bit-clock period at the start of each
frame.
SSPSCLK varies for each protocol as follows:
• For Microwire, both transmit and receive data sources switch data on the falling edge of
SSPSCLK, and sample incoming data on the rising edge.
• For SSP, transmit and receive data sources switch data on the rising edge of SSPSCLK, and
sample incoming data on the falling edge.
• For SPI, the user has the choice of which edge of SSPSCLK to use for switching outgoing
data, and for sampling incoming data. In addition, the user can move the phase of SSPSCLK,
shifting its active state one-half period earlier or later at the start and end of a frame.
While SSP and SPI are full-duplex protocols, Microwire uses a half-duplex master-slave
messaging protocol. At the start of a frame, a 1 or 2-byte control message is transmitted from the
controller to the peripheral. The peripheral does not send any data. The peripheral interprets the
message and, if it is a READ request, responds with requested data, one clock after the last bit of
the requesting message. Return data (part of the same frame) can be from 4 to 16 bits in length.
Total frame length is 13 to 33 bits.
The serial clock (SSPSCLK) only toggles during an active frame. At other times it is held in an
inactive or idle state, as defined by its specified protocol.
8.4.1.1 SSP Format Details
When outgoing data in the SSP controller is ready to be transmitted, SSPSFRM is asserted for one
clock period. On the following clock period, data to be transmitted is driven on SSPTXD one bit at
a time, most significant bit first. Similarly, the peripheral drives data on the SSPRXD pin. Word
length is from 4 to 16 bits. All transitions take place on the SSPSCLK rising edge and data is
sampled on the falling edge. At the end of the transfer, SSPTXD retains the value of the last bit sent
(bit 0) through the next idle period. If the SSP Port is disabled or reset, SSPTXD is forced to zero.
Figure 8-1 shows the Texas Instruments’ Synchronous Serial Frame* format for a single
transmitted frame and when back-to-back frames are transmitted. When the bottom entry of the
transmit FIFO contains data, SSPSFRM is pulsed high for one SSPSCLK period and the value to
be transmitted is transferred from the transmit FIFO to the transmit logic’s serial shift register. On
the next rising edge of SSPSCLK, the most significant bit of the 4 to 16-bit data frame is shifted to
the SSPTXD pin. Likewise, the most significant bit of the received data is shifted onto the
SSPRXD pin by the off-chip serial slave device. Both the SSP and the off-chip serial slave device
then latch each data bit into their serial shifter on the falling edge of each SSPSCLK. The received
data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSPSCLK
after the last bit has been latched.