Intel PXA255 - Manual (Page 133)

Intel® PXA255 Processor Developer’s Manual 4-29
System Integration Unit
In addition to the RCNR, the RTC incorporates a 32-bit, RTC Alarm register (RTAR). The RTAR
may be programmed with a value that is compared against the RCNR. One 32-kHz cycle after each
rising edge of the HZ clock, the counter is incremented and then compared to the RTAR.
If the
values match, and the enable bit is set, then the RTC Status register (RTSR) alarm match bit
(RTSR[AL]) is set. This status bit is also routed to the interrupt controller and may be unmasked in
the interrupt controller to generate a processor interrupt. Another available interruptible status bit
that can be set whenever the HZ clock transitions is the RTSR. By writing a one to the AL or HZ
bit in the RTSR, the status bit is cleared.
The HZ clock is generated by dividing one of two selectable clock sources, both approximately
32.768 kHz in frequency. The first source is the output of the 3.6864 MHz crystal oscillator further
divided by 112 to approximately 32.914 kHz. The other source is the optional 32.768 kHz crystal
oscillator output itself. Your system may be built with both the 32.768 kHz crystal oscillator and
the 3.6864 MHz crystal oscillator. ALternately, your system may only use the 3.6864 MHz crystal
oscillator, if the additional power consumption during sleep mode is acceptable.
The divider logic for generating the HZ clock is programmable. This lets you trim the counter to
adjust for inherent inaccuracies in the crystal’s frequency and the inaccuracy caused by the division
of the 3.6864 MHz oscillator which yields only an approximate 32 kHz frequency. The trimming
mechanism lets you adjust the RTC to an accuracy of +/- 5 seconds per month. The trimming
procedure is described in a later paragraph.
All registers in the RTC, with the exception RTTR, are reset by hardware reset and the watchdog
reset. The trim register, RTTR is reset only by hardware reset.
4.3.2 RTC Register Definitions
The following sections provide register descriptions for the RTC.
4.3.2.1 RTC Trim Register (RTTR)
Program the RTTR to set the frequency of the HZ clock. The reset value of this register
(0x0000_7FFF) (assuming a perfect 32.768 kHz crystal) would produce an HZ clock output of
exactly 1 Hz. However, by using values other than 0x0000_7FFF, a different HZ clock frequency is
possible. Additionally, developers can use a crystal that is not exactly 32.768 kHz and compensate
by writing a value other than 0x0000_7FFF to the RTTR.
Section 4.3.3 describes how to calculate
the value in this register. A write to the RTTC will increment the RTC Count Register (RCNR) by
one. RTTC[LCK] does not prevent the RCNR from incrementing.
All reserved bits must be written to zeros and reads to these bits must be ignored. You can only
reset the RTTR with a hardware reset. To safeguard the validity of the data written into the trim
register, bit 31 is used as a Lock Bit. The data in RTTR may be changed only if RTTR[LCK] is
cleared. Once, RTTR[LCK] is set to be a one, only a hardware reset can clear the RTTR.