Intel PXA255 - Manual (Page 576)

17-6 Intel® PXA255 Processor Developer’s Manual
Hardware UART
17.4.2.3 FIFO DMA Mode Operation
The UART has two DMA requests: one for transmit data service, and one for receive data service.
DMA requests are generated in FIFO mode only. The requests are activated by setting
IER[DMAE].
• Data Transmit Data Service – When IER[DMAE] is set, if the transmit FIFO is less than half
full, the transmit-DMA request is generated. The DMA controller then writes data to the FIFO.
For each DMA request, the DMA controller can send 8, 16, or 32 bytes of data to the FIFO.
The actual number of bytes to be transmitted is programmed in the DMA controller.
• Data Receive Data Service – When IER[DMAE] is set, the receive-DMA request is
generated when the receive FIFO reaches its trigger threshold with no errors in its entries. The
DMA controller then reads data from the FIFO. For each DMA request, the DMA controller
can read 8, 16, or 32 bytes of data from the FIFO. The actual number of bytes to be read is
programmed in the DMA controller along with the bus width.
17.4.2.4 DMA Receive Programming Errors
If the DMA channel stops prematurely, because it encounters the end of a descriptor chain or other
error, the processor must be notified, since the DMA controller can no longer service the UARTs
FIFOs. If this occurs, the processor must correct the situation by programming another descriptor
or by servicing the FIFOs via interrupt or polling modes as previously described. The DMA must
set DCSR[StopIrqEn] to generate an interrupt if a stopped channel occurs.
17.4.2.5 DMA Error Handling
An error interrupt is used when DMA requests are enabled. The interrupt is generated when LSR
bit 7 is set to 1. This happens when a receive DMA request is not generated and the receive FIFO
has an error. The error interrupt tells the processor to handle the data in the receive FIFO through
programmed I/O. The error interrupt is enabled when DMA requests are enabled and cannot be
masked. Receiver line status interrupts occur when the error is at the front of the FIFO.
Note: When DMA requests are enabled and an interrupt occurs, software must first read the LSR to
verify an error interrupt exists, then check the IIR for the source of the interrupt. If an interrupt
occurs and LSR[FIFOE] is clear, software must read the ISR to determine the error condition.
When the last error byte is read from the FIFO, DMA requests are automatically enabled. Software
is not required to check for the error interrupt if DMA requests are disabled. Error interrupts only
occur when DMA requests are enabled.
If an error occurs while in DMA mode:
• receive-DMA requests are disabled
• error interrupt IIR[IID] is generated
The processor must now read the error bytes through programmed I/O. When all errors have been
removed from the FIFO, the receive DMA requests are once again enabled automatically by the
UART.
If an error occurs when the receive FIFO trigger threshold has been reached, such that a receive
DMA request is set, users need to wait for the DMA to finish the transfer before reading out the
error bytes through programmed I/O. If not, FIFO underflow could occur.