Intel PXA255 - Manual (Page 357)

Intel® PXA255 Processor Developer’s Manual 10-1
UARTs
10
This chapter describes the universal asynchronous receiver/transmitter (UART) serial ports. The
serial ports are controlled via direct memory access (DMA) or programmed I/O. The PXA255
processor has four UARTs: Full Function UART (FFUART), Bluetooth UART (BTUART),
Standard UART (STUART) and Hardware UART (HWUART). The HWUART is covered in
Chapter 17. The UARTs use the same programming model.
10.1 Feature List
The UARTs share the following features:
• Functionally compatible with the 16550
• Ability to add or delete standard asynchronous communications bits (start, stop, and parity) in
the serial data
• Independently controlled transmit, receive, line status, and data set interrupts
• Programmable baud rate generator that allows the internal clock to be divided by 1 to (2
16
–1)
to generate an internal 16X clock
• Modem control pins that allow flow control through software. Each UART has different
modem control capability.
• Fully programmable serial-interface:
— 5-, 6-, 7-, or 8-bit characters
— Even, odd, and no parity detection
— 1, 1.5, or 2 stop bit generation
— Baud rate generation up to 921 Kbps for the BTUART and HWUART. Up to 230 Kbps
for other UARTs.
• 64-byte transmit FIFO
• 64-byte receive FIFO
• Complete status reporting capability
• Ability to generate and detect line breaks
• Internal diagnostic capabilities that include:
— Loopback controls for communications link fault isolation
— Break, parity, and framing error simulation
• Fully prioritized interrupt system controls
• Separate DMA requests for transmit and receive data services
• Slow infrared asynchronous interface that conforms to the Infrared Data Association (IRDA)
standard